Xilinx 7 Series

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 269
UG482 (v1.9) December 19, 2016
0012 9:7 R/W SATA_BURST_VAL 2:0 0-7 0-7
0012 6:0 R/W RXOOB_CFG 6:0 0-127 0-127
0013 14:9 R/W SAS_MIN_COM 5:0
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont’d)
DRP
Address
DRP Bits R/W Attribute Name
Attribute
Bits
Attribute
Encoding
DRP
Encoding
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