Xilinx 7 Series User Manual

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 113
UG482 (v1.9) December 19, 2016
TX Phase Interpolator PPM Controller
TX Phase Interpolator PPM Controller Use Mode
The following describes a sample use case:
• A frequency counter in the fabric determines the lead/lag relationship between the two clocks
of interest and increments or decrements (TXPIPPMSTEPSIZE[4]) PI code by a certain step
size (TXPIPPMSTEPSIZE[3:0]).
• A sampler and lock detect circuit in the fabric determines when the two clocks are phase
aligned. When not phase aligned, the user asserts a signal to the TX phase interpolator PPM
controller with the desirable PI code.
This continual phase shifting (fine-tuning) occurs when the lock detect circuit deems the two clocks
out of phase and enables the TX phase interpolator PPM controller.
TXPI_INVSTROBE_SEL 1-bit Binary Reserved. Tied to 1'b0.
TXPI_GREY_SEL 1-bit Binary 1'b0: TXPIPPMSTEPSIZE[3:0] is binary
encoded.
1'b1: TXPIPPMSTEPSIZE[3:0] is grey encoded.
TXPI_PPMCLK_SEL String Reserved. The GT Wizard’s default value should be
used for this attribute.
Table 3-27: TX Phase Interpolator PPM Controller Attributes (Cont’d)
Attribute Type Description
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Xilinx 7 Series Specifications

General

Brand	Xilinx
Model	7 Series
Category	Computer Hardware
Language	English