Xilinx VC709 - Page 31

VC709 Evaluation Board www.xilinx.com 31
UG887 (v1.0) February 4, 2013
Feature Descriptions
• Contains 4 GTH transceivers for PCIe lanes 4–7
•Quad 115:
• MGTREFCLK0 - No clock
• MGTREFCLK1 - PCIe edge connector clock
• Contains 4 GTH transceivers for PCIe lanes 0–3
•Quad 117:
• MGTREFCLK0 - No clock
• MGTREFCLK1 - No clock
• Contains 2 GTH transceivers for FMC1 HPC (DP8–DP9)
•Quad 118:
• MGTREFCLK0 - FMC1 HPC GBTCLK1
• MGTREFCLK1 - FMC1 HPC GBTCLK0
• Contains 4 GTH transceivers for FMC1 HPC (DP4–DP7)
•Quad 119:
• MGTREFCLK0 - No clock
• MGTREFCLK1 - No clock
• Contains 4 GTH transceivers for FMC1 HPC (DP0–DP3)
Table 1-19 lists the GTH interface connections to the FPGA (U1).
Table 1-9: GTH Interface Connections to the FPGA (U1)
Transceiver Bank Net Name Connections
MGT_BANK_113 GTHE2_CHANNEL_X1Y15 SFP/SFP+ 4
GTHE2_CHANNEL_X1Y14 SFP/SFP+ 3
GTHE2_CHANNEL_X1Y13 SFP/SFP+ 2
GTHE2_CHANNEL_X1Y12 SFP/SFP+ 1
MGTREFCLK0 Si5324 jitter attenuator
MGTREFCLK1 SMA_MGT_REFCLK
MGT_BANK_114 GTHE2_CHANNEL_X1Y19 PCIe4
GTHE2_CHANNEL_X1Y18 PCIe5
GTHE2_CHANNEL_X1Y17 PCIe6
GTHE2_CHANNEL_X1Y16 PCIe7
MGTREFCLK0 NC
MGTREFCLK1 NC
MGT_BANK_115 GTHE2_CHANNEL_X1Y23 PCIe0
GTHE2_CHANNEL_X1Y22 PCIe1
GTHE2_CHANNEL_X1Y21 PCIe2
GTHE2_CHANNEL_X1Y20 PCIe3
MGTREFCLK0 NC