Xilinx Virtex-4 User Manual

52 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
SGMII/1000BASE-X PCS/PMA
In SGMII or 1000BASE-X PCS/PMA mode, an entire data stream received from
PHYEMAC#RXD is passed on to EMAC#CLIENTRXD with some latency. This includes
the code group described in Table 3-1. The assertion of EMAC#RXCLIENTDVLD indicates
the position of the first destination address byte all the way to the last byte of the payload.
Figure 3-16 and Figure 3-17 show the timing of a normal inbound frame transfer in SGMII
and 1000BASE-X PCS/PMA mode.
Figure 3-16: Inbound Frame Transfer (Front)
CLIENTEMAC#RXCLIENTCLKIN
PRE
PREAMBLE
TL
DA SA Data
/I1/ /I2/ /I2/ /I2/ /I2/ /S/
PHYEMAC#RXCHARISCOMMA
PHYEMAC#RXCHARISK
PHYEMAC#RXD[7:0]
EMAC#CLIENTRXD[7:0]
EMAC#RXCLIENTDVLD
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
EMAC#CLIENTRXSTATS[6:0]
EMAC#CLIENTRXSTATSVLD
UG074_3_18_072705
Figure 3-17: Inbound Frame Transfer (Back)
CLIENTEMAC#RXCLIENTCLKIN
PREAMBLE DA
DATA
SA
TL
Data
PHYEMAC#RXCHARISCOMMA
PHYEMAC#RXCHARISK
PHYEMAC#RXD[7:0]
EMAC#CLIENTRXD[7:0]
EMAC#RXCLIENTDVLD
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
EMAC#CLIENTRXSTATS[6:0]
EMAC#CLIENTRXSTATSVLD
UG074_3_19_072705
110 20 30 40
FCS /I1/ /R//T/
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English