Xilinx Virtex-4 - Page 82

82 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
A timing diagram for writing to the Address Filter Registers is the same as the one shown
for writing to the Ethernet MAC Configuration Registers (Figure 3-40).
Table 3-18: Multicast Address Table Access (Word 0)
MSB
LSB
313029282726252423222120191817161514131211109876543210
0x388 MULTICAST_ADDRESS[31:0]
Bit Description Default Value R/W
[31:0]
Multicast Address [31:0]. The multicast address bits [31:0] are temporarily
deposited into this register for writing into a multicast address register.
All 0sR/W
Table 3-19: Multicast Address Table Access (Word 1)
MSB
LSB
313029282726252423222120191817161514131211109876543210
0x38c
RESERVED
RNW
RESERVED
ADDR
MULTICAST_ADDRESS[47:32]
Bit Description Default Value R/W
[15:0]
Multicast Address [47:32]. The multicast address bits [47:32] are temporarily
deposited into this register for writing into a multicast address register.
All 0sR/W
[17:16]
Multicast Address: This 2-bit vector is used to choose the multicast address
register to access.
00 = Multicast Address Register 0
01 = Multicast Address Register 1
10 = Multicast Address Register 2
11 = Multicast Address Register 3
All 0sR/W
[22:18] Reserved. –
[23]
Multicast address read enable (RNW): When this bit is 1, a multicast address
register is read. When this bit is 0, a multicast address register is written with
the address set in the multicast address table register.
0 R/W
[31:24] Reserved. –
Table 3-20: Address Filter Mode
MSB
LSB
313029282726252423222120191817161514131211109876543210
0x390
PM
RESERVED
Bit Description Default Value R/W
[30:0] Reserved. –
[31]
Promiscuous Mode enable: When this bit is 1, the Address Filter
block is disabled. When this bit is 0, the Address Filter block is
enabled.
1: When TIEEMAC#CONFIGVEC[64]
is set to 0
0: When TIEEMAC#CONFIGVEC[64]
is set to 1
R/W
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