FLOPPY DISK INTERFACE
When
writing
to
tracks
with
a
track
number
greater
than
43,
the
encoding
circuit
provides
automatic
write
precompensation.
The
precompensation
value
is
set
by a
potentiometer
(WPW), located
on
the
System
Board.
The
decoding
section
of
the
disk controller circuitry
decodes
the
MFM encoded data from
the
Raw Read input,
during transfer operations from
the
disk.
The
decoder is a
phase-locked loop
data
separator
circuit
based around
an
internal
voltage controlled oscillator (VCO)
and
phase
detector.
The
centre
frequency of
the
VCO is
set
by
a
variable capacitor (VCl), located
on
the
System
Board. A
second variable
control
RPW sets
the
read
window
pulse
width.
The
head
positioning
control
section
responds to
the
head
positioning
commands
supplied to
the
Command
Register
and
controls
the
STEP and
Direction
(DIRC)
outputs.
The
rate
at
which
the
2
JLS
step
pulses are issued to
the
drive,
to
move
the
head from track-to-track is specified
by
the
command.
Issuing a step pulse
to
the
drive to
move
the
head towards
Track
a,
automatically
decrements
the
Track Register. Issuing a
step
pulse to
the
drive
to
move
the
head away
from
Track
a,
automatically
increments
the
Track Register.
The
status
monitoring
section
monitors
the
logic
state
on
the four
inputs
from
the
disk drive, READY, TRaG, Index
Pulse (IP)and
Write
Protect
(WPRT). All
the
four
inputs
can
be
monitored
by
issuing
any
of
the
head
positioning
commands
or
the
Force
Interrupt
command,
and
then
examining
the
contents
of
the
Status Register.
The
effect of
the
status
inputs
on
the
operation of
the
FDC
is
dependent
on
the
command
issued
to
the
Command
Register
and
the
logic
state
of
the
input
line.
Command Register
The
8-bit
Command
Register holds
the
command
supplied from
the
CPU
which
determines
the
type of
operation carried
out
by
the
FDC,
and
is
located
at
address
location
4GH
in
the
I/O
space.
The
register
can
only
be
written
to
with
one
of eleven predefined
command
words. A
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