ACT apricot - Read Register Definition

SERIAL INTERFACE
DTR (D7). This bit controls the modem control output Data
Terminal Ready (DTR). When the DTR bit is set to logic
high,
the DTR output is set to the active state (logic low).
When reset to logic low, the DTR output is reset to the
inactive logic high state.
Write Register 6
I
07
1
06
1
05
1
04
1
03
1
02
1 01 1 DO 1
WR6
I I I
Sync bits/Address
Write Register 6 is programmed with:
(a) The transmit sync character in Monosync.
(b) The 8 LSB of the 16-bit sync character in Bisync.
(c) The 8-bit frame address byte in bit oriented modes.
Write Register 7
I
07
1
06
1
05
1
04
1
03
1
02
1 01 I DO I
WR7
I I
.... I------Sync bits/Flag
Write Register 7 is programmed with:
(a) The receive sync character in Monosync.
(b) The 8 MSB of the 16-bit sync character in Bisync.
(c) A flag character in bit oriented modes .
. Read Register Definition
Both channels contain two Read Registers each (RRO and
RRl), which define· the status within the channel. A third
Read Register (RR2) accessed through channel B contains a
copy of
the interrupt vector, which indicates the SIO
interrupt routine (if any), currently in service.