ACT apricot - Processor Interface

SERIAL INTERFACE
The transmitter section of the serial channels, consist of
an 8-bit data register (the transmit buffer), supplied with
character data from the processors, and a 20-bit transmit
shift register. The shift register converts the parallel data in
the transmit buffer into serial format and also performs a
variety of other functions depending on the mode of
operation.
In
the asynchronous mode, the data from the transmit
buffer is automatically formatted with start, stop and parity
bits within the shift register, prior to transmission.
In
Monosync and Bisync, the shift register is loaded with
the sync characters stored in the Write Registers, at the
beginning of the message, and then data from the transmit
buffer as transmission proceeds. The shift register also
supplies
the serial data to the CRC generator, which
produces the two byte CRC at the end of the message.
In the bit oriented modes, the shift register is loaded with
the flags stored in the Write Register, at the beginning and
end of the message. The shift register supplies the serial
data
to the CRC generator which generates the 2-byte CRC
at the end of the data field, and to the transmit data output.
For character lengths of less than 8 bits, the characters
sent to the transmit buffer have to be right justified, by the
programmer. The logic state of the unused bits within each
character byte (MSB) are immaterial for character lengths of
6
and 7 bits, since the extra bits are automatically ignored
by
the SIO. For a 5-bit character, the unused bits have to be
programmed with logic O's. Character lengths of less than 5
bits require a combination of logic l's and logic O's, to be
inserted in the MSB as detailed in a later section.
Processor Interface
The connections to the SIO processor interface are
detailed
in the table "System Connections" at the end of the
section. The interface handles the transfer of data,
commands and status information (via the 8-bit bi-
directional peripherals
data bus), between the processors
and the series of addressable registers within the SIO.