ACT apricot - Interrupt Sequence

INTERRUPT CONTROLLER
The system software views the PIC as two input/output
ports, with each port able to accept and provide a vari~of
data bytes. The port address locations, defined by the PIC
select line and the system bus connection, together with the
abbreviations of the data bytes are given below. A detailed
explanation of
the data can be found in the
PROGRAMMING CONSIDERATIONS section following.
Port Address
Data Bytes Transfer Operation
0
IRR/ISR
Read
0
ICWl/OCW2/0CW3
Write
1
IMR
Read
1
OCWI/ICW2/ICW4
Write
Interrupt Sequence
The interrupt sequence, entered on receipt of a logic high
on any of the interrupt request lines of the PIC is described
in the following paragraphs. This sequence is the same
regardless of the actual PIC interrupt request line being set
active.
When one or more of the interrupt request lines are set
into the active high state, corresponding bits in an 8-bit
internal register within the PIC (the Interrupt Request
Register-IRRj are also set.
The PIC selects the highest
priority bit stored in the IRR, which is not masked by the
software, for comparison with bits stored in a second 8-bit
register (the
Interrupt Service Register-ISRj, to determine
whether an interrupt should be issued to the CPU.
The Interrupt Service Register contains bits which
indicate the interrupt service routines currently being
executed
by the CPU. If the highest priority unmasked
interrupt request is of a higher priority than the highest
priority
bit set within the ISR, the interrupt control line to
the CPU is set into the active state. If the highest priority
unmasked interrupt request is not of a higher priority than
the highest priority bit within the ISR, no further action
takes place. The priority of the interrupt requests is
determined by the priority mode selected.