ACT apricot - SIO Architecture

SERIAL INTERFACE
The SIO can also be programmed to generate interrupts to
signal to the processors the status of various transmit and
receive conditions in the two communication channels.
These include, receive data available, transmit data
required, and the detection of various error conditions.
The interrupt structure of the SIO is such that on
generating an interrupt to the CPU, it can also produce an
interrupt vector internally, which defines the cause of the
interrupt. This can then be used by the CPU to point to an ~
associated service routine. The vector is obtained from the
SIO by performing an interrupt acknowledge cycle.
The interrupt method of communication between the
SIO and the CPU is the one adopted on the System Board.
The SIO only generates an interrupt to the CPU when the
device requires a specific servicing routine to be carried out,
leaving
the processors free to service the other devices on
the board.
The SIO interrupt is not wired directly to the CPU but is
supplied
via the Interrupt Controller (PIC). The PIC
provides a vector to the CPU to indicate the device
generating
the interrupt. If the device is the SIO, the actual
process within the device requiring attention is then
specified by the interrupt vector from the SIO.
SIO Architecture ~
Internally, the SIO consists of four areas of circuitry:
(a) A Processor interface.
(b) Internal interrupt control logic.
(c) The two independent full duplex serial
communication channels, channel A and channel B.
The processor interface handles all communications via
the data bus between the processors and a series of internal
registers, associated with each of the two serial channels.
These are of three different types; data registers, command
registers and status registers.
Both channels have two data registers each, which are