ACT apricot - General; Screen Ram

Display
Enable
Cursor
LPSTB
CRT CONTROL
Output generated by the CRTC which defines
the active scan line/retrace periods of the
electron beam. Logic high indicates the active
periods, logic low the retrace periods. Supplied
to the Parallel Interface, the video interface and
the memory control circuits.
Output signal supplied to the video interface,
used to control the cursor on the-screen in the
text mode. Every time the CR TC produces a
refresh address
which matches the cursor
address programmed into control registers R14
and R1S, the cursor output is set to logic high,
producing a positive going pulse for one CCLK
period.
Light
Pen Strobe input. Connected to a Molex
connector (LP) on the System Board. Allows a
light pen and associated control circuitry or
similar device to be connected to the CR TC.
Every time a positive edge is generated on this
input, the current refresh address is latched
into control registers R16 and R17.
SCREEN RAM
General
The Screen RAM consists of two 2k x 8 bit static RAMs
arranged
in a 2k x 16 bit block and occupies 4 Kbytes in the
system memory space at address location FOOOOH to
FOFFFH (2048 16-bit words). The RAM is dual port
memory, being able to be accessed by both the processors
and the CRTC. Access to the RAM is controlled by a
memory contention circuit. The memory contention circuit
guarantees the CRTC access to the RAM once every
character clock period to refresh the screen. Wait states are
automatically added to the processor memory cycle, if the
processors attempt to access the RAM, during a CR TC
access (1 to 3 wait states in text mode, 1 to 5 wait states in
graphics).