ACT apricot - Page 84

CRT CONTROL
E
RES
CCLK
MAO to
MAIO
RAO to
RA3
VSYNC
HSYNC
Enable input. Data strobe signal for latching
data to/from the peripherals data bus. Logic
high to low transition at the end of the second
processor clock cycle after the address is valid.
Input signal to reset the CRTC. Active state,
logic low.
Generated by the Parallel Interface.
When active, all counters within the CRTC are
cleared and all outputs are forced to logic low.
The contents of the registers are unaffected.
Character clock. Input signal from the timing
circuit, with a 50% duty cycle, derived from
the 15 MHz dot clock. Used as the basic CRTC
timing signal. In text mode, the frequency is 1.5
MHz. In graphics, 937.5 kHz.
Refresh memory address signals. Address
outputs, which change every character clock
period during the active scan line period to
access the Screen RAM and thus refresh the
CRT screen.
Raster address signals. Address lines to the
System RAM to select a row within a character
font cell to be displayed in text mode, a row
within the graphics cell image in the graphics
mode.
Sync pulses supplied to the Display Unit to
control the retrace of the electron beam back to
the top of the screen at the end of each active
field period. Pulses are generated at a rate of
approximately 72 Hz.
Sync pulses supplied to the Display Unit to
control the horizontal sweep of the beam across
the screen during the active field period. The
pulses are generated at a scan rate of 15.79 kHz.
continued ....