ACT apricot - Parallel Interface Interrupts

SERIAL INTERFACE
D7
DO
I 1 I 1 I 0 I x I x I x I x I 1 I Write Register 3
~
LRxEnable
Auto Enables off
8 bitsjRx character
D7 DO
I x I x I x 11 11 11 I 0 I 0 I Write Register 1
L
L Ext. Interrupt masked
(Parallel Interface
interrupts)
Tx Interrupt Enabled
Status affects vector
Rx Interrupts Enabled
PARALLEL INTERFACE INTERRUPTS
Three printer control output lines from the Parallel
Interface (Fault, Acknowledge and Busy) are wired to the
SIO channel B modem control inputs (SYNCB, CTSB and
DCDB respectively). These inputs can be programmed to
generate an interrupt to the CPU, every time a transition
occurs on any of the printer lines. The logic state on all
three printer inputs are also indicated by a corresponding bit
within Read Register O.
The logic states of the bits in the register can only be
regarded as reflecting the true state of the printer lines, if
prior to reading the register, a reset external/status
command is issued to Write Register o. The bits within the
register indicate the inverse of the logic state on the control
input.
To enable transitions on the three inputs to generate an
interrupt, requires the external/status interrupt bit
originally set to logic 0 during channel B initialisation, to be
updated. This is achieved by reprogramming bit DO of Write
Register 1 to logic 1.