ACT apricot - SIO Interrupt Sequence

SERIAL INTERFACE
SIO Interrupt Sequence
The SIO incorporates an elaborate interrupt structure,
which acts as an extension to the interrupt structure
provided by the Interrupt Controller (PIC) on the System
Board. A single
interrupt output line (INT) connects the SIO
to the PIC.
Each channel within the SIO is able to generate an
interrupt for a variety of conditions. All interrupting
sources can be enabled or disabled (masked) by software,
and are ordered
on a priority basis. All sources within
Channel A are assigned a higher priority than Channel B.
Wi thin each channel, the assigned priori ty is as detailed
below:
1. Special receive condition (Highest).
2. Receive character available.
3.
External/status interrupt.
4. Transmit data required (Lowest).
If a SIO interrupt is in service when a higher priority
interrupt condition occurs, the higher priority condition is
granted service.
The SIO stores the lower priority condition
and
resumes the interrupt service routine on completion of
the higher priority interrupt routine.
A special receive
interrupt is generated when the SIO
detects any of the following conditions in the receive data:
1. Parity errors.
2. Receiver overrun.
3. Framing errors (asynchronous modes).
4. End of Frame (SDLC/HDLC only).
Receive
character available interrupts can be programmed
to generate
an interrupt on every receive character or for the
first character only (synchronous modes).