ACT apricot - Page 159

SERIAL INTERFACE
condi tion un til reset by loading the error reset command
into Write Register O.
CRC/Framing Error (D6). The function of this bit is
dependent on the mode selected. In asynchronous modes,
the bit is set to logic high on detecting a receive character
with incorrect stop bits (framing error). The error condition
only persists for the particular character stored in the
receive buffer. In synchronous modes, the bit indicates the
result from the receive CRC error detection circuit. A logic
high indicates a CRC error. The error conditions are reset to
the inactive low state after issuing the error reset command
to Write Register O.
End of Frame (D7). In the bit oriented modes, this bit
indicates that a valid closing £lag has been detected and the
CRC Error and residue codes are now valid. The bit is reset
by issuing an error reset command to WRO.
Read Register 2
I D71 D61 D51 D41 D3
1
D21 Dl I DO I
RR2
I I
r-.
I
_______ Interrupt Vector
(channel B only')
Read Register 2 contains the interrupt vector and is read
through channel B only. If the status affect vector bit is set
(D2, Write Register 1), the register indicates the current
interrupt service routine (if any) in operation, and is a copy
of
the interrupt vector supplied to the CPU. If no interrupts
are pending, the vector is set to the condition for a special
receive
condition in channel B (see Write Register 1
description).
If the status affect vector bit is not set (logic
low),
the register contains a copy of the vector written into
Write Register 2 in channel B. .