ACT apricot - Page 158

SERIAL INTERFACE
removed. In the bit oriented modes, the bit is set ~o logic
high
on detecting an abort sequence in the receive data. The
bit is reset to logic low on loading Write Register a with the
reset external/status command. The bit is not used in the
byte· oriented synchronous modes.
Read Register 1
Pa
rity Error
Rx Dve
rrun Error
CRC/Framin
g Error
End of Frame (SDLC)
All Sent (DO). In asynchronous modes, this bit is set to logic
high
when all the bits of the character have been
transmitted onto the serial link. In synchronous modes the
bit is permanently set to logic high.
Residue Codes
(Dl to D3). The combination of these three
bits indicate the length of the I-field in the bit oriented
modes
where the I -field is not an integral multiple of the
character length.
Parity Error (D4). When parity is enabled, this bit is set to
logic high on detecting a receive character whose parity
does
not match the sense programmed by bit 1 of Write
Register
4. The bit remains set in the error condition until
reset by loading the error reset command into Write
RegisterO.
Rx Overrun Error (D5). This bit is set to logic high when one
or
more receive characters have been overwritten in the
receive FIFO buffer. The bit remains set in the error