ACT apricot - Page 157

SERIAL INTERFACE
buffer. It is reset to the logic low inactive state by reloading
the transmit buffer with a new data character.
DeD (D3). The DCD bit indicates the state of the modem
control input Data Carrier Detect (DCD). This state is
latched every time any external/status interrupt condition
occurs, and remains in the latched state until reset by
writing the reset external/status interrupt command to
Write Register O. Therefore, to ensure that the current state
of the DCD input is obtained, the bit should be read,
immediately following a reset external/status interrupt
command. The DCD bit indicates the inverse of the state on
the DCD input.
Sync/Hunt (D4). In asynchronous modes, this bit indicates
the state of the Sync input and operates in a similar manner
to the DCD bit, with regard to the latching process. The
Sync bit indicates the inverse of the state on the Sync input.
In
synchronous modes, the bit reflects the phase of the
synchronous receive operation. Initiating the Hunt phase
causes
the bit to be set to logic high. (i.e. On reset or setting
the enter hunt mode bit in Write Register 3). On achieving
character
synchronisation, the bit is set to logic low as the
receive phase begins and remains in this condition unless
the Hunt phase is initialised again.
eTS (D5). This bit functions in a similar manner to the
DCD bit with regard to the latching process, but indicates
the inverse of the state on the Clear to Send input (CTS).
Transmit Underrun/EOM (D6). In synchronous modes, the
bit is set to logic high following a system/channel reset,
allowing sync/flag
characters to be sent when the transmit
buffer becomes empty. When the reset transmit underrun/
EOM command is issued to Write Register 0, the transmit
underrun/EOM bit is set to logic low. This enables CRC
characters to be automatically sent instead of the sync/flag
characters.
Break/Abort
(D7). In asynchronous modes, this bit is set to
logic high, when a break is detected in the receive data. The
bit is not reset until, a reset external/status command is
issued
to Write Register 0 and the break condition is