ACT apricot - General; Interrupt Masking; Programming Considerations

INTERRUPT CONTROLLER
Providing the software controlled interrupt-enable flag of
the CPU is enabled, the CPU acknowledges the interrupt,
by issuing two Interrupt Acknowledge pulses (INTApulses)
to the PIC, via the 8288 Bus Controller. The first INTA
pulse latches the highest priority interrupt request from the
IRR through to the ISR. The second INTA pulse enables
vectoring
data associated with the highest priority bit
within the ISR onto the system data bus.
The vectoring data (designated an interrupt number) is a
single software defined byte,
which is used by the CPU to
specify the address location of the corresponding service
routine. On completion of the service routine, the
associated ISR bit within the Interrupt Service Register is
reset
under software control.
Interrupt Masking
Masking any of the interrupt requests is achieved under
software control by utilising a third internal8-bit register
located
within the PIC, known as the Interrupt Mask
Register (IMR). The 8-bits within the IMR directly
correspond
to the 8-bits within the Interrupt Request
Register.
Setting an IMR bit prevents the PIC actioning any
active state on the associated interrupt request line.
PROGRAMMING CONSIDERATIONS
General
Before the PIC can operate normally within the
processing system, it has to be initialized with a series of
command words which define the required operating mode,
the vectoring data and the initial priority of the interrupt
request inputs.
Once initialised, the operation of the PIC can be modified
and controlled by a second series of command words which:
(a) Enable the interrupt request lines to be individually
masked.
(b) Allow the ISR bits within the Interrupt Service
Register to be cleared at the end of an interrupt service
routine.