ACT apricot - Page 161

SERIAL INTERFACE
An external/status interrupt can be caused by any of the
following conditions:
1. Transitions on the modem control lines; DCD, CTS
and SYNC.
2. A break in receive data (asynchronous modes).
3.
An abort sequence in receive data (bit synchronous
modes).
4.
Transmit underrun/EOM condition in transmit data
(synchronous modes).
The actual sequence of events performed on the
occurrence of a SIO interrupt condition is as follows.
The SIO compares the new interrupt with any interrupt
currently in service. If the new interrupt is of a higher
priority than the current interrupt, the INT output is set
active (logic low). If the new interrupt is of a lower priority,
the interrupt condition is stored until it becomes the
highest priority.
The INT output, after inversion, forms the interrupt
request line (IRS) to the PIC. Providing IRS is the highest
priority unmasked interrupt request to the PIC, an interrupt
is issued to the CPU. The CPU determines the device
generating
the interrupt by performing a PIC interrupt
acknowledge sequence, which then provides an associated
interrupt vector.
For
the CPU to determine the SIO process generating the
interrupt, the CPU has to perform a special SIO interrupt
acknowledge sequence. This is achieved by issuing a
"locked" read cycle, as defined by the following 8086
instruction:
LOCK IN AL,60H
This instruction accesses the SIO interrupt vector, which
is a base address previously supplied to the SIO, modified
according
to the condition generating the interrupt. The SIO
interrupt, thus allows the CPU to select the appropriate
interrupt service routine. On -completion of the SIO service
routine,
the CPU has to issue a return from interrupt