ACT apricot - Page 199

EXPANSION SLOTS
AIOWC Advanced Input/Output Write Command.
Output from the 8288 Bus Controller. Active
low control signal which is set active before
the Input/Output Write Command to
provide
input/output devices an earlier
indication of a write cycle.
IOWC Input/Output Write Command. Output from
the 8288 Bus Controller. Active low write
command for input/output devices.
MRDC Memory Read Command. Output from the
8288 Bus Controller. Active low read
command for memory-mapped devices.
IORC Input/Output Read Command. Output from
the 8288 Bus Controller. Active low read
command for input/output devices.
MRDY Memory Ready. Input connected to the
8284A Clock Generator (RDY2) via an AND
gate. Normally at logic high, but is set low to
command the processing elements to extend
the control transfer commands, by inserting
wait states, until the selected memory-
mapped device is ready for the data transfer
operation. MRDY returning to logic high
indicates that the selected memory-mapped
device is ready for the data transfer operation
(read or write).
IORDY Input/Output Ready. Input connected to the
8284A Clock Generator (RDYl) via an AND
gate. Normally at logic high, but is set low to
command the processing elements to extend
the control transfer commands, by inserting
wait states, until the selected input/output
device is ready for the data transfer
operation. IORDY returning to logic high
indicates that the selected input/output
device is ready for the data transfer operation
(read or write).
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