ACT apricot - Page 50

INTERRUPT CONTROLLER
CHANNEL 1 INTERRUPT
IRO INT
INTERRUPT T[] CPU
FROM IDP (8089 SINTRD
(8086 INTR)
CHANNEL 2 INTERRUPT
IRl
INTA
INTERRUPT ACKNOWLEDGE
FROM IDP (8089 SINTR2) VIA BUS CONTROLLER (INTA)
EXPANSION SLOT
IR2
INTERRUPT (INT2)
DO
EXPANSION SLOT
IR3
TO SYSTEM DATA BUS
INTERRUPT (INT3)
prc
D7
FLOPPY DISK CONTROLLER
INTERRUPT (FDC INT)
IR4
8259A
WR:RIi SYSTEM CONTROL BUS <AI~~.~):=
SERIAL INTERFACE
IR5
INTERRUPT <SID INT)
TIMER COUNTER 0
IR6 cs
PIC SELECT
OUTPUT <TMR OUTO)
AO Al
INTERRUPT FROM
IR7
NDP (8087 INT>
Figure 1. Interrupt Controller block diagram
PIC Pin Definition
IRDtoIR7
INT
INTA
DDtoD7
RI5
WR
CS
AD
Interrupt Request inputs
Interrupt output
Interrupt Ackno-wledge
Data bus connection
Read control line
Write control line
Chip select input
System address bus input