ACT apricot - Page 55

INTERRUPT CONTROLLER
Since the PIC has to respond to a level sensitive interrupt
request and there is only one PIC, the format of ICWl is
fixed as detailed below.
The address location ICWl is
written to, is OOH in the system input/output space.
D7 DO
x indicates that the logic state is immaterial
program to zero.
The function of ICW2 is to define a base address for the
interrupt number. This is signified by five bits within the
control word. The three other bits required to form the
whole interrupt number (the 3 least significant bits - LSB)
are auto.matically inserted by the PIC and are dependent on
the interrupt request line as detailed below.
IR
T2 Tl TO
0 0 0 0
1
0 0
1
2
0 1 0
3
0 1 1
4
1
0
0
5
1
0
1
6
1 1
0
7 1 1 1
T* = Interrupt Number bit
The base address of the eight interrupt numbers assigned
to
the PIC is SOH as defined by the ICW2 format below. The
I/O address location ICW2 is written to, is 02H.
T7 T6 T5 T4 T3
The interrupt number associated with each interrupt
request line is generated by combining the base address (the
S
most significant bits - MSB of the interrupt number) with
the bits automatically inserted by the PIC (the 3LSB). This