ACT apricot - Page 60

TIMER
CK2 OUT2
r----., I
I 4 MHz I I I
I
OSC ~ DIVIDER :
CKI OUTI
IO,25MHz
CKO OUTO
- - - - - - - -------\1 DO
_____ ~E~IPHERALS DATA BUS TO T M R
D7 8253-5
~Y~T~~ ~O~T§O-L-B-U-S -(l=O=RC-',A-ro-W-C--"')I Ri),WR
TMR SELECT CS
A2 Al
Al AO
~
SELECTABLE
CLOCKS FOR
SERIAL
INTERFACE
(SID TXCA/RXCA)
TIMER
OUTPUT TO
INTERRUPT
CONTROLLER
(PIC IR6)
Figure I.Programmable Interval Timer block diagram
TMR Pin Definition
CKO
CKI
CK2
OUT 0
OUT 1
OUT 2
DOtoD7
RD
WR
CS
AO,AI
DESCRIPTION
General
Clock input for Counter 0
Clock input for Counter 1
Clock input for Counter 2
Output from Counter 0
Output from Counter 1
Output from Counter 2
Data bus connection
Read control line
Write control line
Chip select input
System address bus inputs
The timer is organized internally as three independent
I6-bit counters, each with an associated control word
register which determines the operating mode of the I6-bit
counter.
The counters count down on the negative edge of
the respective clock pulse input. .