CRT
CONTROL
period,
the
screen address (cell
pointer
combined
with
raster
address lines) and
the
processors are allowed
acce~s
to
the
System
memory.
During
the
flyback periods,
the
processors
are still allowed access,
but
the
screen address is
inhibited
and
the
memory
control refresh
counter
enabled.
The
refresh
counter
provides addresses to perform
the
hardware
refresh of
the
System
memory
dynamic
RAMs.
Supplying
the
DE signal
to
the
Parallel Interface enables
the
processors
to
detect
the
active
and
flyback periods as
required.
Cursor
movement
in
the
text
mode, is controlled by
changing
the
contents
of a
pair
of registers
within
the
CRTC,
which
specify
the
cursor
position
on
the
screen.
The
cursor
is
displayed
by
the
CRTC,
supplying a cursor display
signal (cursor)
to
the
video interface as
the
electron
beam
sweeps
the
required
cursor
character
position
on
the
screen.
In graphics mode,
the
cursor
display signal is
inhibited
at
the
video interface.
The
CR
TC
contains
a
pair
of registers
which
define
the
height
of
the
text
cursor,
and
also provide
an
optional
facility to allow
the
cursor
to
blink
at
one of
two
different
rates.
The
width
of
the
text
cursor
is fixed and corresponds
to
the
width
of a
character
cell
(10
pixels).
Scrolling of
the
screen
is
achieved by writing a different
start
address
into
another
pair of registers located
internally
within
the
CR TC.
The
start
address
is
the
first refresh
memory
address to be supplied
to
the
Screen RAM,
at
the
start
of
each
field period.
The
CRTC
also provides a facility
to
connect
a
light
pen
with
its
associated
control
electronics, for detecting
the
electron
beam
as
it
scans across
the
screen.
NOTE:
The
standard 9
inch
green
on
black Apricot Display
Unit
utilises a long persistence phosphor (P39),
which
may
not
support
the
use of a light pen interface.
Internally
the
CRTC
consists
of a collection of registers,
counters'and
comparators,
which
time
all
the
logic .
activities (generation of addresses, sync. pulses, etc.) as
the
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