ACT apricot - Page 95

FLOPPY DISK INTERFACE
e MHz
r--, r---,\
1 4 MHz ~ DIVIDER
L ES£ -' L ___ -'
PERIPHERALS DATA BUS
= S~STEM CONTROL BUS (ICWEJilRC)
~
AI!
WD
DIRe
C~~ FDC SSo
WD2797-02
DO
RAW RD
TO
TROQ
D7
if
READY
W£.RE
WPiff
Cs
A1
14----1 BUFFERS
FLOPPY DISK
CONNECTOR
DRIVE SELECT 0
DRIVE SEJ..ECT 1
Al AO
DRQ
1----+ DMA REQUEST TO THE IDP (1lJP DRQ1)
SYSTEM RESET (~)
iii
INTRa
FROM CLOCK GEIiERA TOR
Figure 1. Floppy Disk Interface block diagram
FDC
Pin Definition
WD
Write Data
DRQ Data Request
WG
Write Gate
INTRQ
Interrupt Request
STEP
Step
pulse output
CLK
Clock input
DIRC
Direction control DOtoD7
Data bus
SSO
Side Select
Output
WE
Write Enable
RAWRD
Read Data RE
Read Enable
TROO
Track 00
CS
Chip Select
IP
Index Pulse
AO , Al
Register selects
READY
Ready
input MR
Master Reset
WPRT
Write Protect