Programmer’s Guide 5-3
Using Status Registers
General Status Register Model
General Status Register Model
The analyzer's status system is based on the general status register
model shown in Figure 5-1. Most of the analyzer's register sets include
all of the registers shown in the model, although commands are not
always available for reading or writing a particular register. The
information flow within a register set starts at the condition register and
ends at the register summary bit (see Figure 5-2 on page 5-5 for actual
connections between the registers). This flow is controlled by setting bits
in the transition and enable registers.
Two register sets — the Status Byte and the Standard Event Status
Register — are 8-bits wide. All others are 16-bits wide, but the most
significant bit (bit 15) in the larger registers is always set to 0.
Figure 5-1 General Status Register Model
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