5-4 Programmer’s Guide
Using Status Registers
General Status Register Model
Condition Register
Condition registers continuously monitor the instrument's hardware and
firmware status. Bits in a condition register are not latched or buffered,
they are updated in real time. When the condition monitored by a specific
bit becomes true, the bit is set to 1. When the condition becomes false,
the bit is reset to 0. Condition registers are read-only.
Transition Registers
Transition registers control what type of change in a condition register
will set the corresponding bit in the event register. Positive state
transitions (0 to 1) are only reported to the event register if the
corresponding positive transition bit is set to 1. Negative state
transitions (1 to 0) are only reported if the corresponding negative
transition bit is set to 1. Setting both transition bits to 1 causes both
positive and negative changes to be reported. Transition registers are
read-write, and are unaffected by *CLS (clear status) or queries. They
are reset to instrument default conditions at power up and after *RST
and SYSTem:PRESet commands.
Event Register
Event registers latch any reported condition changes. When a transition
bit allows a condition change to be reported, the corresponding event bit
is set to 1. Once set, an event bit is no longer affected by condition
changes. It remains set until the event register is cleared. Event
registers are read-only.
An event register is cleared when you read it. All event registers are
cleared when you send the *CLS (clear status) command.
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