Allen-Bradley SLC 500 Series - Page 688

Publication 1747-RM001G-EN-P - November 2008
6 Index
major error halted bit B-12
manuals, related P-2
Masked Move (MVM)
updates to arithmetic status bits
5-18
math instructions 4-2
32-Bit addition and subtraction 4-6
about 4-2
Absolute (ABS) 4-24
Add (ADD) 4-5
Arc Cosine (ACS) 4-29
Arc Sine (ASN) 4-29
Arc Tangent (ATN) 4-30
changes to the math register 4-3
Clear (CLR) 4-12
Compute (CPT) 4-25
Cosine (COS) 4-30
Divide (DIV) 4-9
Double Divide (DDV) 4-11
instruction parameters 4-2
Log to the Base 10 (LOG) 4-31
Multiply (MUL) 4-8
Natural Log (LN) 4-31
overflow trap bit 4-3
overview 4-2
ramp 4-20
Scale Data (SCL) 4-15
Scale with Parameters (SCP) 4-13
Sine (SIN) 4-32
Square Root (SQR) 4-12
Subtract (SUB) 4-5
Swap (SWP) 4-28
Tangent (TAN) 4-32
updates to arithmetic status bits 4-3
using arithmetic status bits 4-5, 4-8,
4-9, 4-11, 4-12, 4-14, 4-16,
4-24, 4-26, 4-29, 4-30, 4-31,
4-32, 4-33, 5-2, 5-5, 5-9,
5-10, 5-12
using indexed word addresses 4-2
X to the Power of Y (XPY) 4-33
math overflow selection bit 4-6, B-17
math register B-37
maximum observed DII scan time B-57
memory module
boot bit
B-23
data file overwrite protection B-53
password mismatch bit B-23
program compare B-16
memory usage C-1
fixed and SLC 5/01 C-2
overview C-1
SLC 5/02 C-7
SLC 5/03, 5/04, 5/05 C-13
message
instruction (SLC 5/02 processor)
12-5
instruction error codes 12-41
reply pending (channel 0) B-46
servicing selection (channel 0) B-47
servicing selection (channel 1) B-48
messaging examples 15-1
minor error bits B-21
mnemonic, using
in logical addresses
E-6
Modbus to MicroLogix memory map
13-96, 13-97
modems
dial-up phone
13-84
leased-line 13-84
line drivers 13-85
radio 13-85
monitoring index addresses E-13
Move (MOV)
updates to arithmetic status bits
5-17
move and logical instructions
changes to the math register
5-17
indexed addressing 5-16
instruction parameters 5-16
updates to arithmetic status bits 5-16
MSG Instruction
Parameters
12-11
MSG instruction 13-49
for a 5/02
communication instruction
12-5
for SLC 5/03 and SLC 5/04 processors
communication instruction
12-5
Multiply (MUL) 4-8
math instruction 4-8
N
NAK retries
SLC 5/03, 5/04 or 5/05
13-52
Natural Log (LN) 4-31
math instruction 4-31
Negate (NEG)
updates to arithmetic status bits
5-24
nesting subroutine files 6-4
Not (NOT)
updates to arithmetic status bits
5-23
Not Equal (NEQ) 3-2
comparison instruction 3-2
number systems E-18
binary numbers F-1
hex mask F-5
hexadecimal numbers F-3