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General| Programming Software | RSLogix 500 |
|---|---|
| Series | SLC 500 |
| Category | Controller |
| Manufacturer | Allen-Bradley (Rockwell Automation) |
| I/O Capacity | Up to 4096 I/O points |
| Communication Ports | DH-485 |
| Programming Languages | Ladder Logic |
| Operating Temperature | 0 to 60 °C (32 to 140 °F) |
| Relative Humidity | 5% to 95% (non-condensing) |
| Memory | 4K to 64K words (depending on the processor) |
| Power Supply | AC or DC (depending on the module) |
Identifies the target audience for this manual, including designers, installers, programmers, and troubleshooters of SLC 500 systems.
Defines the manual as a reference guide for SLC 500 controllers, covering status file functions and ladder logic instructions.
Lists related Rockwell Automation documents for additional information on SLC 500 products and solid-state control considerations.
Explains conventions used throughout the manual, such as bulleted lists for information and numbered lists for sequential steps.
Describes the SLC 500 user memory structure, comprising Data Files and Program Files, and default file types.
Explains Data Files 0 and 1 represent external outputs and inputs, detailing the addressing format for outputs and inputs.
Details the fixed Status File (S:2), its addressing format, and examples of accessing its bits and words.
Describes the bit file (File 3), its maximum size, and addressing formats for bits and elements.
Explains timer instructions use 3-word elements (Word 0: status, Word 1: preset, Word 2: accumulator) and provides addressing format.
Details how to address bits and words using the format Tf:e.s/b for timers.
Describes counter addresses as 3-word elements (Word 0: control, Word 1: preset, Word 2: accumulator) and status bits.
Details parameters for Counter instructions, including Accumulator Value (ACC) and Preset Value (PRE), and addressing structure.
Explains the use of control bits in 3-word elements for various instructions and the structure of control elements.
Describes how to assign integer addresses as 1-word elements, addressable at the element and bit level.
Explains float data type addresses as 2-word elements, addressable at the element level.
Introduces basic instructions that represent hardwired logic circuits and are separated into three groups: bit, timer, and counter.
Explains that bit instructions operate on a single bit of data and are used with Output/Input Files, Status File, Bit File, and Timer File.
Describes the XIC instruction for determining if a bit is ON, evaluating the instruction as true if the bit is addressed as ON (1).
Describes the XIO instruction for determining if a bit is OFF, evaluating the instruction as true if the bit is addressed as OFF (0).
Explains the OTE instruction to turn a bit ON or OFF when rung conditions are true. OTE instructions are reset under specific conditions.
Describes OTL and OTU as retentive output instructions that turn a bit ON or OFF respectively, retaining state.
Explains the OSR instruction as a retentive input instruction that triggers an event to occur one time based on rung state change.
Provides general information about timer instructions and how they function, detailing parameters like Accumulator Value and Preset Value.
Describes the TON instruction to turn an output on or off after a preset time interval, counting timebase intervals when rung conditions are true.
Explains the TOF instruction to turn an output on or off after its rung has been off for a preset time interval.
Describes the RTO instruction to turn an output on or off after its timer has been on for a preset time interval, retaining accumulated value.
Explains how counters work, including the count value range and status bits for overflow (OV) or underflow (UN).
Describes the CTU instruction that counts false-to-true rung transitions, incrementing the accumulated value by one.
Explains the CTD instruction that counts false-to-true rung transitions, decrementing the accumulated value by one.
Introduces the HSC as a variation of the CTU counter that counts high-speed pulses from a fixed controller's high-speed input.
Explains the RES instruction used to reset a timer or counter, clearing accumulated value and status bits.
Explains that comparison instructions test pairs of values to condition rung continuity; if the first value meets the condition, the instruction is true.
Describes the EQU instruction to test if two values are equal, evaluating as true if equal and false otherwise.
Explains the NEQ instruction to test if two values are not equal, evaluating as true if not equal and false if equal.
Describes the LES instruction to test if one value is less than another, evaluating as true if A < B, and false otherwise.
Explains the LEQ instruction to test if one value is less than or equal to another, evaluating as true if A <= B, and false otherwise.
Describes the GRT instruction to test if one value is greater than another, evaluating as true if A > B, and false otherwise.
Explains the GEQ instruction to test if one value is greater than or equal to another, evaluating as true if A >= B, and false otherwise.
Describes the MEQ instruction to compare data at a source address with data at a compare address, using a mask.
Explains the LIM instruction to test values within or outside a specified range, depending on how limits are set.
Introduces math instructions that perform arithmetic functions, taking two input values and outputting the result to an assigned memory location.
Provides general information applicable to all math instructions, including source, destination, and operand types.
Details parameters for math instructions, including source (address/constant), destination (address), and support for floating point/string values.
Explains the option of using indexed word addresses for instruction parameters specifying word addresses.
Describes using indirect word-level and bit-level addresses for instructions specifying word addresses.
Explains that arithmetic status bits are in the controller status file (Word 0, bits 0-3) and are updated after instruction execution.
Describes the minor error bit (S:5/0) set upon detection of mathematical overflow or division by zero.
Explains that S:13 and S:14 contain the 32-bit signed result of MUL, DIV, and DDV instructions.
Describes the Float data file type valid for SLC 5/03 and higher, as 2-word elements addressable at the element level.
Explains the ADD instruction to add two values (source A and B) and place the result in the destination.
Describes the SUB instruction to subtract source B from source A and place the result in the destination.
Explains the option of performing 16-bit or 32-bit signed integer addition and subtraction using status file bit S:2/14.
Details how to set S:2/14 for 32-bit operations and the resulting overflow bit and destination address behavior.
Describes the MUL instruction to multiply one value (source A) by another (source B) and place the result in the destination.
Explains that S:13 and S:14 contain the unrounded quotient and remainder for DIV and DDV instructions.
Describes the DIV instruction to divide one value (source A) by another (source B), placing the rounded quotient and remainder.
Explains the DDV instruction to divide the 32-bit math register by a 16-bit source value, placing the rounded quotient in the destination.
Describes the CLR instruction to set the destination value of a word to zero.
Explains the SQR instruction to calculate the square root of the absolute value of the source and place the rounded result in the destination.
Describes the SCP instruction to produce a scaled output value with a linear relationship between input and scaled values.
Details the parameters for SCP: Input value, Input Min/Max, Scaled Min/Max, and Scaled Output.
Explains the SCL instruction where the source value is multiplied by the rate value, added to the offset, and placed in the destination.
Describes the RMP instruction for creating linear, acceleration, deceleration, and 'S' curve ramp output waveforms.
Explains the ABS instruction to calculate the absolute value of the source and place the result in the destination.
Describes the CPT instruction for performing copy, arithmetic, logical, and conversion operations by defining an expression.
Explains the SWP instruction to swap the low and high bytes of a specified number of words in various file types.
Describes the ASN instruction to take the arc sine of a number and store the result (in radians) in the destination.
Explains the ACS instruction to take the arc cosine of a number (source in radians) and store the result in the destination.
Describes the ATN instruction to take the arc tangent of a number (source) and store the result (in radians) in the destination.
Explains the COS instruction to take the cosine of a number (source in radians) and store the result in the destination.
Describes the LN instruction to take the natural log of the value in the source and store the result in the destination.
Explains the LOG instruction to take the log base 10 of the value in the source and store the result in the destination.
Describes the SIN instruction to take the sine of a number (source in radians) and store the result in the destination.
Explains the TAN instruction to take the tangent of a number (source in radians) and store the result in the destination.
Describes the XPY instruction to raise a value (source A) to a power (source B) and store the result in the destination.
Lists data handling instructions with their mnemonic, name, purpose, and page number.
Explains the TOD instruction to convert 16-bit integers into BCD values.
Details how arithmetic status bits in the controller status file (Word 0, bits 0-3) are updated after instruction execution.
Describes the FRD instruction to convert BCD values to integer values.
Explains the DEG instruction to convert radians to degrees and store the result in the destination.
Describes the RAD instruction to convert degrees to radians and store the result in the destination.
Explains the DCD instruction sets one bit of the destination word based on the first four bits of the source word.
Describes the ENC instruction to search the source for the first set bit and write its position to the destination.
Explains COP instruction copies data blocks and FLL instruction loads values into a file.
Describes the MOV instruction to move source value to the destination location, repeating each scan the rung remains true.
Explains the MVM instruction to move data from source to destination, allowing portions to be masked by a separate word.
Describes the AND instruction for a bit-by-bit logical AND operation using source A and source B values.
Explains the OR instruction for a bit-by-bit logical OR operation using source A and source B values.
Describes the XOR instruction for a bit-by-bit logical XOR operation using source A and source B values.
Explains the NOT instruction for a bit-by-bit logical NOT operation using the value at source A.
Describes the NEG instruction to change the sign of the source and place it in the destination.
Introduces FIFO (First In First Out) and LIFO (Last In First Out) instructions for loading and unloading words into files.
Lists program flow instructions with mnemonic, instruction name, purpose, and page number.
Explains that control instructions manage program sequence, allowing changes to scan order to minimize scan time and troubleshoot.
Describes JMP and LBL instructions used in pairs to skip portions of the ladder program, saving scan time or executing segments repeatedly.
Explains JSR, SBR, and RET instructions for executing separate subroutine files and returning to the instruction following JSR.
Describes MCR instructions used in pairs to create program zones that turn off non-retentive outputs within the zone.
Explains the TND instruction stops processor scanning for the rest of the program file, updates I/O, and resumes scanning at rung 0.
Describes the SUS instruction that causes the processor to enter Suspend Idle mode, storing the Suspend ID in S:7.
Explains the IIM instruction allows data update prior to the normal input scan, transferring data through a mask to the input data file.
Describes the IOM instruction to update outputs prior to the normal output scan, transferring data through a mask to the physical output.
Explains the REF instruction interrupts the program scan to execute the I/O scan and service communication portions.
Lists application specific instructions with mnemonic, instruction name, purpose, and page.
Explains that these instructions simplify ladder programs by performing complex operations with single instructions or pairs.
Provides general information applicable to bit shift instructions.
Describes BSL as an output instruction that loads data into a bit array one bit at a time, shifting data to the left.
Explains BSR as an output instruction that loads data into a bit array one bit at a time, shifting data to the right.
Provides general information applicable to sequencer instructions.
Describes SQO instruction that transfers 16-bit data to word addresses for sequential machine operations.
Explains SQC instruction that transfers 16-bit data to word addresses for sequential machine operations, comparing to a reference word.
Describes the SQL instruction that stores 16-bit data into a sequencer load file at each step of sequencer operation.
Explains the RHC instruction provides a high performance timestamp for diagnostics and calculations.
Describes the TDF instruction to calculate the number of 10 µs ticks between any two timestamps captured using the RHC instruction.
Explains the FBC instruction used to monitor operations to detect malfunctions by comparing bits in a file to a reference file.
Describes the DDT instruction used to monitor operations to detect malfunctions, comparing bits and changing reference bits on mismatch.
Explains the RPC instruction copies the program checksum from processor RAM or memory module to a destination integer file.
Lists block transfer instructions with mnemonic, instruction name, purpose, and page.
Explains BTR (Block Transfer Read) and BTW (Block Transfer Write) instructions for transferring data over RIO link.
Describes how RIO scanners perform block transfers using control/status buffers in M0 and M1 files.
Details parameters for BTR/BTW: Data File, BTR/BTW Buffer File, and Control.
Explains how to examine instruction control and status bits stored in the control structure, mapped to bits in Word 0.
Details the sequential processing of BTR/BTW instructions by the scanner and SLC control program.
Provides examples of block transfer programming, referencing figures for different modes like Directional and Repeating.
Compares BTR/BTW instructions in SLC processors to PLC-5, highlighting differences in Control Block, Error Codes, and limitations.
Describes the PID instruction as an output instruction controlling physical properties using process loops, typically with analog I/O.
Explains PID closed loop control, holding a process variable at a desired set point, with examples of flow rate/fluid level control.
Presents the standard PID equation with dependent gains, used to control processes by sending output signals to the control valve.
Shows a PID instruction with typical addresses and parameters, emphasizing integer-only algorithm and rung logic placement.
Details entering parameters for PID: Control Block, Process Variable, and Control Variable addresses.
Presents the PID control block layout, fixed at 23 words, detailing flags and parameters like Setpoint, Gain, and Reset.
Describes the Controller Gain (Kc) parameter, affecting proportional gain and its range.
Explains the Reset Term (Ti) as the integral gain, ranging from 0 to 3276.7 minutes per repeat.
Describes the Rate Term (Td) as the derivative term, adjustment range 0 to 327.67 minutes.
Explains how bias can be added to the CV output using the Feed Forward/Bias element for anticipation of disturbance.
Describes the Mode bit specifying PID operation in timed mode (1) or STI mode (0), affecting CV updates.
Explains Loop Update (Word 13) as the time interval between PID calculations, in 0.01 second intervals.
Describes Deadband (DB) as extending above and below the setpoint, affecting operation only after the process variable enters the deadband.
Defines Scaled Error as the difference between process variable and setpoint, with format determined by the Control Mode (CM) bit.
Explains the Auto/Manual bit, specifying automatic operation (0) or manual operation (1), controlling the control variable (CV).
Describes the Control Mode bit, toggling E=SP-PV and E=PV-SP, affecting control variable increase or decrease relative to setpoint.
States this bit is set (1) when the process variable is within the zero-crossing deadband range.
Explains the RG bit affects reset minute/repeat and gain multiplier values, dividing them by 10 when set (1).
Notes the SC bit is cleared when setpoint scaling values are specified.
Explains the TF bit is set if the loop update time cannot be achieved by the controller due to scan time limitations.
Describes the DA bit, which when set (1), evaluates derivative calculation on error; when clear (0), evaluates on process variable.
States the control variable upper limit alarm bit is set (1) when calculated CV output exceeds the upper CV limit.
Explains the control variable lower limit alarm bit is set (1) when calculated CV output is less than the lower CV limit.
This bit is set (1) when the setpoint exceeds the maximum scaled value or is less than the minimum scaled value.
The process variable out of range bit is set (1) when the unscaled process variable (PV) exceeds 16,383 or is less than zero.
The PID done bit is set (1) for one scan when the PID algorithm is computed; it resets automatically.
When RA bit is set, rational approximation method is used for PID computation, resulting in more accurate output.
The PID enabled bit is set (1) whenever the PID instruction is enabled. It follows the rung state.
This is the result of the integration of the error term over time.
Shows input parameter addresses, data formats, and user program access types.
The SP (Setpoint) is the desired control point of the process variable.
The SPV (Scaled Process Variable) is the analog input variable; range is SMIN to SMAX if scaling is enabled.
Corresponds to the setpoint value in engineering units when the control input is at its maximum.
Corresponds to the setpoint value in engineering units when the control input is at its minimum.
Lists output parameter addresses, data formats, and user program access types.
The CV (Control Variable) is user-defined and represents the PID output value.
Displays the control variable as a percentage (0 to 100%), tracking CV in auto mode or manipulated value in manual mode.
A value of one enables output limiting to CVH (Max) and CVL (Min); a value of zero disables OL.
When OL is enabled, CVH is the maximum output (in percent). If CV exceeds CVH, CV is set to CVH, and UL bit is set.
When OL is enabled, CVL is the minimum output (in percent). If CV is below CVL, CV is set to CVL, and LL bit is set.
Lists PID instruction runtime errors, their descriptions, probable causes, and corrective actions.
Lists ASCII instructions with mnemonic, instruction name, purpose, and page number.
Describes ASCII instructions available in SLC 5/03+ processors, categorized into port control and string control.
Lists ASCII protocol parameters configurable via Channel 0 settings: Baud Rate, Start Bits, Stop Bits, Parity, Data Bits, Termination, Append.
Explains that ASCII data file types are 1-word elements and provides the addressing format (Af:e/b).
Describes the ST data file type for SLC 5/03+ processors, 42-word elements, with string length and data access via .DATA[n].
Details the control element parameters for ASCII instructions, including status bits, error code byte, and character words.
Explains the ABL instruction to determine total characters in input buffer up to end-of-line characters.
Describes the ACB instruction to determine total characters in the buffer, recording value in the position field.
Explains the ACI instruction to convert a numeric ASCII string to an integer value between -32,768 and 32,767.
Describes the ACL instruction to clear ASCII buffers immediately upon rung transition to true.
Explains the ACN instruction to combine two strings using ASCII operands, appending the second string to the first.
Describes the AEX instruction to create a new string by taking a portion of an existing string.
Explains the AHL instruction to set or reset RS-232 DTR and RTS handshake control lines for a modem.
Describes the AIC instruction to convert an integer value to an ASCII string.
Explains the ARD instruction to read characters from the buffer and store them in a string.
Describes the ARL instruction to read characters from the buffer up to and including end-of-line characters, storing them in a string.
Explains the ASC instruction to search an existing string for an occurrence of the source string.
Describes the ASR instruction to compare two ASCII strings for length and case sensitivity.
Explains the AWA instruction to write characters from a source string to an external device, adding configured append characters.
Describes the AWT instruction to write characters from a source string to an external device.
Lists ASCII instruction error codes and their recommended actions.
Lists interrupt routine instructions with mnemonic, instruction name, purpose, and page.
Explains the user fault routine option to prevent processor shutdown on specific user faults.
Details data saved on entry to user fault subroutine and rewritten upon exit: S:0, S:13/14, S:24.
Provides steps to create a user fault subroutine, specifying file number in S:29 and using S:20/S:21 for fault location.
Presents an example of controlling major errors (0020h, 0034h) by preventing shutdowns or resetting accumulator values.
Explains the STI function to interrupt processor scan periodically to scan a subroutine file.
Provides steps for STI function: create subroutine file, enter STI file number in S:31, and setpoint in S:30.
Describes STI subroutine content, allowing most instructions except TND, REF, SVC; requires IIM/IOM for immediate I/O update.
Defines interrupt latency and shows interaction between interrupt and processor operating cycle.
Lists interrupt priorities for SLC 5/03 and higher processors: User Fault, DII, STI, I/O Interrupt.
Details data saved on entry to STI subroutine and rewritten upon exit: S:0, S:13/14, S:24.
Explains STD (Selectable Timed Disable) and STE (Selectable Timed Enable) instructions used to create zones where STI execution is controlled.
Describes STD resets STI enable bit, preventing subroutine execution; timer continues to operate.
Explains STE sets STI enable bit on false-to-true transition, allowing subroutine execution.
Provides a ladder program example showing STD and STE instructions to avoid STI subroutine execution at specific points.
Describes STS instruction to condition STI timer start upon REM Run mode entry, or to set file number/setpoint.
Explains DII for high-speed applications or event response, allowing subroutine execution when input bit pattern matches a programmed value.
Details steps for DII function: create subroutine file, enter Slot number (S:47), Bit Mask (S:48), Compare Value (S:49), Preset Value (S:50), File Number (S:46).
Describes DII operation after download and REM Run mode entry, including Counter Mode and Event Mode.
Explains DII subroutine content, allowing most instructions except TND, REF, SVC; requires IIM/IOM for immediate I/O.
Defines interrupt latency and shows interaction between DII and processor operating cycle.
Lists interrupt priorities for SLC 5/03 and higher: User Fault, DII, STI, I/O Interrupt.
Details data saved on entry to DII subroutine and rewritten upon exit: S:0, S:13/14, S:24.
Explains DII reconfigurability through parameter changes and the use of reconfiguration bits.
Details DII parameters with status file addresses: Pending Bit, Enable Bit, Executing Bit, Overflow Bit, Reconfigure Bit, Lost Bit, File Number, Slot Number, Bit Mask, Compare Value, Preset, Return Mask, Accumulator.
Lists communication instructions with mnemonic, instruction name, purpose, and page.
Introduces SLC communication instructions, including Service Communication, Message Read/Write, CEM, DEM, and EEM.
Explains the SVC instruction interrupts program scan to execute service communication portion of operating cycle.
Describes MSG instruction operation, allowing read/write data between nodes and holding multiple messages enabled.
Lists configuration options for MSG on SLC 5/02+ processors: Peer-to-peer Read/Write on local/remote networks.
Details parameters for MSG instruction: Read/Write, Target Device, Local/Remote, Control Block, Control Block Length, Setup Screen.
Shows control block layouts for 500CPU/PLC-5, 485CIF, and PLC-5 with Logical ASCII/Symbolic Addressing.
Lists status bits associated with MSG instruction: Timeout (TO), Error (ER), Done (DN), Enabled (EN), Waiting for Queue Space (WQ).
Discusses limitations for manipulating MSG instruction control block values, highlighting CO, EN, and TO bits as manipulable.
Introduces CEM, DEM, EEM instructions for initiating generic CIP commands to devices on ControlNet, DeviceNet, EtherNet/IP networks.
Details parameters for CEM instruction: Control Block and Control Block Length.
Lists parameters for CEM setup screens: Parameters for This Controller (General Tab) and Parameters for Target Device (General Tab).
Explains DEM instruction for initiating unconnected CIP Generic messages via 1747-SDN DeviceNet scanner module.
Details parameters for DEM instruction: Control Block and Control Block Length.
Lists parameters for DEM setup screens: Parameters for This Controller (General Tab) and Parameters for Target Device (General Tab).
Describes EEM instruction for initiating connected CIP Generic messages via channel 1 on SLC 5/05 processor.
Details parameters for EEM instruction: Control Block and Control Block Length.
Lists parameters for EEM setup screens: Parameters for This Controller (General Tab).
Lists supported communication drivers (DH-485, DH+, Ethernet, DF1, Modbus RTU, ASCII) and their capabilities per SLC processor.
Provides an overview of DH-485, DH+, and Ethernet protocols, including their features and capabilities.
Details DH-485 network features, protocol, token rotation, and considerations for performance.
Describes the protocol used for message transfers on DH-485, supporting initiators and responders with token passing.
Explains network initialization process starting with link dead timeout and token claiming.
Lists major configuration factors affecting DH-485 network performance: nodes, addresses, baud rate, token hold factor, broadcasting.
Provides steps to configure an SLC processor channel for DH-485 using programming software.
Explains how channel status data is stored and displayed for DH+ communications on SLC 5/04 processors.
Describes SLC 5/05 Ethernet capabilities, network connections, media, node establishment, and configuration.
Discusses factors affecting SLC 5/05 Ethernet performance: message size, frequency, network loading, and application program.
Explains TCP/IP mechanism for Ethernet messages and network setup using hubs or switches.
Provides steps to configure SLC 5/05 processor channel 1 for Ethernet via BOOTP or DHCP, or manually.
Describes DF1 Full-duplex protocol for RS-232 point-to-point communication, supporting simultaneous bidirectional transmission.
Provides steps to configure SLC 5/03, 5/04, or 5/05 processor channel 0 for DF1 full-duplex.
Explains how DF1 Half-duplex Slave channel status data is stored in the diagnostic file.
Describes DF1 Radio Modem driver protocol, optimized for radio networks, hybrid of DF1 full/half-duplex.
Lists questions to answer for implementing DF1 Radio Modem driver: device compatibility, firmware requirements, handshaking, duplex support.
Provides steps to configure SLC 5/03, 5/04, or 5/05 processor channel 0 for DF1 Radio Modem.
Explains Modbus RTU Master protocol for transferring information between data files in Master and Slaves.
Provides steps to configure a channel for Modbus RTU Master using programming software.
Explains how Modbus RTU Master channel status data is stored and displayed.
Summarizes processor OS firmware and passthru capability for SLC 5/03-5/05 across various communication drivers.
Describes SLC processor acting as a bridge between channel 0/1 and remote I/O network via 1747-SN/BSN modules.
Explains DeviceNet passthru via 1747-SDN module, allowing PC communication to devices on DeviceNet network.
Describes channel-to-channel passthru allowing devices on one network to communicate with devices on another via SLC processor bridge.
Lists SLC 5/03 passthru processor error codes (20H, 30H) and their conditions.
Provides procedure to get RSWho to browse from channel 1 through SLC 5/03-5/05, configuring IP address and DF1 passthru enable bit.
Explains SLC 5/05 uses a routing table to cross-reference one-byte addresses with four-byte IP addresses for Ethernet communication.
Illustrates common and elaborate messaging examples using SLC 500 processors.
Explains Local MSG for same-network communication and Remote MSG for cross-network communication via bridge/gateway.
A Local MSG transmits data between processors on the same network.
A Remote MSG exchanges information with devices not on the local network.
Defines Remote Bridge Address, Remote Station Address, and Remote Bridge Link ID.
Illustrates SLC 5/03 passthru processor forwarding messages between DF1 and DH-485 networks.
Shows SLC 5/03 processor forwarding DF1 network messages to DH-485 network as local messages.
Illustrates SLC 5/04 processor messaging to SLC 5/03 via DHRIO and KA5.
Shows SLC 5/03 processor receiving remote messages on DH-485 and forwarding them to DF1 network.
Illustrates SLC 5/03 sending local message via DF1 (CH0) to SLC 5/04 on DH+ network.
Shows SLC 5/03 processor receiving remote messages on DH+ and forwarding them to DH-485 network.
Illustrates SLC 5/05 passthru example: DF1 to Ethernet.
Shows SLC 5/03 sending local message via DF1 to SLC 5/05 (IP Address 100.100.115.9) as bridge.
Illustrates network message example between SLC 5/04 and SLC 5/02 via DHRIO and KA5.
Shows network message example between SLC 5/04 and SLC 5/03 via DHRIO and KA5.
Illustrates network message example between SLC 5/04 and SLC 5/04 via DHRIO.
Shows network message example between SLC 5/04 and SLC 5/02 via KA5.
Illustrates network message example between SLC 5/04 and SLC 5/03 via KA5.
Shows network message example between SLC 5/05 and SLC 5/04 via ENET and DHRIO.
Illustrates network message example between SLC 5/05 and SLC 5/03 via ENET, CNB and KFC.
Shows network message example between SLC 5/05 and SLC 5/04 via ENET, DHRIO and KA5.
Illustrates network message example from PLC 5/20E to SLC 500 CH0 via ENI.
Describes methods to automatically clear faults using programming software, including Fault Override and User Fault Routine.
Explains manual fault clearing using status file bits, keyswitch toggling, or by pressing the clear major fault function key.
Details using the designated subroutine for recoverable faults to correct problems and clear the fault bit S:1/13.
Categorizes processor faults into Powerup errors, Going-to-run errors, Run errors, and User program instruction errors.
Lists powerup errors with Error Codes (Hex), Descriptions, Probable Causes, and Recommended Actions.
Details going-to-run errors with Error Codes (Hex), Descriptions, Probable Causes, and Recommended Actions.
Lists run errors with Error Codes (Hex), Descriptions, Probable Causes, and Recommended Actions.
Details user program instruction errors with Error Codes (Hex), Descriptions, Probable Causes, and Recommended Actions.
Lists I/O errors with Error Codes (Hex), Descriptions, Probable Causes, and Recommended Actions.
Original Release information for OS300, Series A, FRN 1.
Enhancements for OS300, Series A, FRN 2, listing 'None'.
Enhancements for OS300, Series A, FRN 3, including On-Line Editing and Instruction Performance improvements.
Enhancements for OS300, Series A, FRN 4, including ASCII Instructions and Floating Point Instructions support.
Enhancements for OS301, Series A, FRN 5, including Multi-hop Messaging and improvements to diagnostics.
Enhancements for OS302/OS401/OS501 Series C, FRN 3, including added Block Transfer Instructions and PID Rational Approximation.
Enhancements for OS302/OS401/OS501 Series C, FRN 4, including Daughtercard Fault Signal and improvements to Interrupt Performance.
Enhancements for OS302/OS401/OS501 Series C, FRN 5, including additional Ethernet connections and embedded web server.
Enhancements for OS302/OS401/OS501 Series C, FRN 6, including Modbus RTU Master capability and DF1 passthru.
Enhancements for OS302/OS401/OS501 Series C, FRN 7, including channel-to-channel passthru and DF1 radio modem driver.
Enhancements for OS302/OS401/OS501 Series C, FRN 8, including HTTP and SNMP server enable/disable.
Enhancements for OS501, Series C, FRN 9, including Selectively Disabling Individual Data Files from Web View and Secure Processor.
Details firmware history for SLC 5/03, 5/04, and 5/05 processors, listing enhancements by FRN release.
Lists the status file overview, covering processor options, operating system, and fault monitoring.
Provides detailed descriptions of each status word and bit function, indicating processor support and page references.
Explains the status file's purpose: monitoring OS, directing operations via interrupts, loading programs, and monitoring faults.
Details S:0 flags: Carry, Overflow, Zero, Sign, and their behavior during different operations and interrupts.
Explains S:1 bits 0-4 for processor modes: Remote Download, Remote Program, Fault after REM, REM Run, REM Idle, REM Download.
Details processor modes after powerup based on keyswitch position, covering Run, Idle, Program/Download, and Fault states.
Indicates if forces have been enabled in ladder program; bit remains cleared if not enabled.
Indicates if at least one other node is present on the network attached to channel 1.
When set, clears Major Error Halted (S:1/13) and Minor Error bits (S:5/0-7) on power up, attempting REM Run mode.
When set, executes fault routine before first scan if power is cycled after fault. Allows clearing Major Error Halted bit S:1/13.
This bit prevents NVRAM user program modification when set; requires matching memory module for Run mode entry.
Determines STI setpoint timebase: clear for 10 ms increments, set for 1 ms increments.
Indicates DII accumulator equals preset and DII file number is waiting for execution.
Allows DII subroutine execution if DII file number is non-zero; if clear, subroutine does not execute.
Indicates DII interrupt has occurred and subroutine is executing; cleared on completion, power-up, or REM Run entry.
Set to use 32-bit operations; affects overflow bit (S:0/1) and overflow trap bit (S:5/0).
Indicates error when LFU, LFL, FFU, FFL, BSL, BSR, SQO, SQC, SQL instructions generate an error.
Major error code (S:6) indicates major error occurred during fault routine processing.
Lists I/O errors with codes (xx50-xx55, 0056, xx57-xx59, 0x00A0-0x00A2) and their causes/recommendations.
Shows memory capacity for Fixed, SLC 5/01, 5/02, 5/03, 5/04, and 5/05 processors.
Describes SLC 500 controllers' user memory capacities and definitions for calculating memory usage.
Provides memory usage estimates for instructions in Fixed and SLC 5/01 processors.
Provides a step-by-step method to estimate total memory usage for Fixed or SLC 5/01 processors.
Demonstrates calculation of total memory usage for a fixed controller with specific configuration.
Provides an example calculation of memory usage for an SLC 5/01 processor with a specific configuration.
Lists memory usage for instructions specific to SLC 5/02 processors.
Provides a step-by-step method to estimate total memory usage for an SLC 5/02 processor.
Demonstrates calculation of memory usage for an SLC 5/02 processor with a specific configuration.
Compares user word accumulation in SLC 5/03+ processors versus SLC 5/02, noting SLC 5/02 efficiency.
Shows memory usage times for SLC 5/03, 5/04, 5/05 processors, including floating point instructions.
Lists available addressing modes (Direct, Indexed, Indirect) and file types (Output, Input, Status, Bit, Timer, etc.).
Explains direct addressing uses the data stored at the specified address in the instruction.
Describes specifying address with '#' character; processor uses Index Register S:24 to add offset to base address.
Explains specifying address indirectly by replacing file/element/sub-element number with [Xf:e.s] symbol.
Describes combining indirect and indexed addressing; processor resolves indirect address first, then adds offset from S:24.
Explains file instructions use user-created files addressed with '#' sign, storing offset in S:24.
Describes entering numeric constants directly into instructions, with ranges and radix options (integer, binary, ASCII, hexadecimal).
Explains M0/M1 files reside in specialty I/O modules, not processor memory, and can be addressed independently of processor scan.
Provides addressing format Mf:e.s/b for M0/M1 files and restrictions on usage.
Illustrates techniques using ladder diagrams and COP instruction to capture and use M0 or M1 data.
Discusses specialty I/O modules retaining M0-M1 data status after power removal, affecting OTE instruction behavior.
Explains G files used for specialty I/O module configuration, accessed offline via I/O Configuration function.
Details editing G file data offline according to application requirements, using decimal and hex/bcd formats.
Explains processor memory stores 16-bit binary numbers, with each position representing a decimal value based on powers of 2.
Describes positive decimal values, limited to 32767, with the far-left position always being 0.
Explains the use of 2s complement notation for negative values, calculated by subtracting the far-left position's value.
Describes hexadecimal numbers using single characters with equivalent decimal values from 0 to 15, based on powers of 16.
Explains the 4-character hex code used as a parameter to exclude selected bits of a word from instruction operation.
Discusses floating-point arithmetic support for numbers outside -32768 to +32767 range or requiring finer resolution.
Illustrates various instructions using a paper drilling machine example, including tracking drill wear and signaling replacement.
Describes the paper drilling machine operation: book placement, drilling sequence, and conveyor movement.
Explains program logic tracking drilled holes and inches, with pilot lights for drill wear and machine shutdown.
Illustrates the use of TON and SQO instructions in a traffic signal application with specific timing requirements.
Shows how FD bit on SQC can advance SQO to the next step for specific event order requirements.
Illustrates using an input to toggle an output on or off.
Shows interfacing Enhanced Bar Code Decoders to SLC 5/03+ processors via DH-485 using MSG instruction.
Lists read/write commands supported by SLC 500 Fixed, 5/01, 5/02, 5/03, 5/04, 5/05 processors.
Details commands, CMD/FNC, processor support, and addressing modes for read/write operations.
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