Anybus CompactCom M40 User Manual

Host Interface 24 (114)
3.3.4 Memory Access Read Timing
The WE input signal must remain high during a read access. The timing diagram shows a burst
read, but the timing applies for a single read as well. The Anybus CompactCom M40 has no
setup or hold timing requirements on the address bus relative to CS during read operations.
The only limitation on read setup and hold times is that the pingpong and powerup interrupt will
be acknowledged if all address lines are high for 10-15 ns or more while CS is low.
Address
CS
OE
Data
Data valid
Data valid
tAA tAA
tACS
tAR
tHZ
tHZ
Address valid
Address valid
tDH
tRC
Fig. 7
Symbol Parameter Min (ns) Max (ns)
tRC Read cycle time 30
-
tAA Address valid to Data valid
-
30
tACS CS low to Data valid
-
30
tAR OE low to Data valid
-
15
tHZ CS or OE high to output reached tristate
-
15
tDH Data hold time 0
-
Anybus
®
CompactCom
™
M40 Hardware Design Guide HMSI-216-126 EN 2.6

Anybus CompactCom M40 Specifications

General

Brand	Anybus
Model	CompactCom M40
Category	Conference System
Language	English