Introduction
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 1-4
ID073015 Non-Confidential
1.3 Features
The features of the processor include:
• A dual-issue integer unit with integral CoreSight logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible
Interfaces (AXI) for master and slave interfaces.
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack.
• Low interrupt latency.
• Non-maskable interrupt.
• Optional Floating Point Unit (FPU). The Cortex-R4F processor is a Cortex-R4 processor
that includes the FPU.
• A Harvard L1 memory system with:
— optional Tightly-Coupled Memory (TCM) interfaces with support for error
correction or parity checking memories
— optional caches with support for optional error correction schemes
— optional ARMv7-R architecture Memory Protection Unit (MPU)
— optional parity and Error Checking and Correction (ECC) on all RAM blocks.
• The ability to implement and use redundant core logic, for example, in fault detection.
• An L2 memory interface:
— single 64-bit master AXI interface
— 64-bit slave AXI interface to TCM RAM blocks and cache RAM blocks.
• A debug interface to a CoreSight Debug Access Port (DAP).
• A trace interface to a CoreSight ETM-R4.
•A Performance Monitoring Unit (PMU).
•A Vectored Interrupt Controller (VIC) port.
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