ARM Cortex-R4 - 2.4 Operation

Functional Description
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-15
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2.4 Operation
When you power-up the Cortex-R4 processor, you must first reset it. See Clocking and resets
on page 2-11. When it is out of reset, and no longer halted, it starts to fetch and execute
instructions from the reset vector and according to the instruction set. See Reset on page 3-16.
The processor initially fetches instructions from, and transfers data to and from either the TCM
interfaces or the L2 memory interfaces.
The processor also responds to stimulus received on its interfaces, for example interrupts, or
transactions received on the AXI slave interface.
2.4.1 Initialization
Most of the architectural registers in the processor, such as r0-r14, and s0-s31 and d0-d15 when
floating-point is included, are not reset. Because of this, you must initialize these for all modes
before they are used, using an immediate-MOV instruction, or a PC-relative load instruction.
The Current Program Status Register (CPSR) is given a known value on reset. See the ARM
Architecture Reference Manual for more information. The reset values for the CP15 registers
are described along with the registers in Chapter 4 System Control.
In addition, before you run the application, you might want to:
• program particular values into various registers, for example, stack pointers
• enable various processor features, for example, error correction
• program particular values into memory, for example, the TCMs.
The following sections describe other initialization requirements:
• MPU
• FPU
• Caches on page 2-16
• TCM on page 2-16.
MPU
If the processor is built with an MPU, before you can use it you must:
• program and enable at least one of the regions
• enable the MPU in the System Control Register, see c1, System Control Register on
page 4-37.
See c6, MPU memory region programming registers on page 4-51. Do not enable the MPU
unless at least one MPU region is programmed and active. If the MPU is enabled, before using
the TCM interfaces you must program MPU regions to cover the TCM regions to give access
permissions to them.
FPU
If the processor is built with a Floating Point Unit (FPU) you must enable it before VFP
instructions can be executed:
• enable access to the FPU in the coprocessor access control register, see c1, Coprocessor
Access Register on page 4-46
• enable the FPU by setting the EN-bit in the FPEXC register, see Floating-Point Exception
Register, FPEXC on page 11-8.