System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-51
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MCR p15, 0, <Rd>, c5, c1, 0 ; Write ADFSR
MRC p15, 0, <Rd>, c5, c1, 0 ; Read ADFSR
MCR p15, 0, <Rd>, c5, c1, 1 ; Write AIFSR
MRC p15, 0, <Rd>, c5, c1, 1 ; Read AIFSR
c6, Data Fault Address Register
The DFAR characteristics are:
Purpose Holds the address of the fault when a synchronous abort occurs.
Usage constraints The DFAR is:
• a read/write register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes The DFAR bits [31:0] contain the address where the synchronous abort
occurred.
To access the DFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 0 ; Read DFAR
MCR p15, 0, <Rd>, c6, c0, 0 ; Write DFAR
A write to this register sets the DFAR to the value of the data written. This is useful for a
debugger to restore the value of the DFAR.
The processor also updates the DFAR on debug exception entry because of watchpoints. See
Effect of debug exceptions on CP15 registers and DBGWFAR on page 12-45 for more
information.
c6, Instruction Fault Address Register
The IFAR characteristics are:
Purpose Holds the address of the instruction that caused a prefetch abort.
Usage constraints The IFAR is:
• a read/write register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes The IFAR bits [31:0] contain the Instruction Fault address.
To access the IFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 2 ; Read IFAR
MCR p15, 0, <Rd>, c6, c0, 2 ; Write IFAR
A write to this register sets the IFAR to the value of the data written. This is useful for a
debugger to restore the value of the IFAR.
4.3.20 c6, MPU memory region programming registers
The MPU memory region programming registers program the MPU regions.
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