ARM Cortex-R4 - Page 319

Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-45
ID073015 Non-Confidential
Table 12-40 shows the values in the link register after exceptions.
The following sections describe:
• Effect of debug exceptions on CP15 registers and DBGWFAR
• Avoiding unrecoverable states.
12.7.1 Effect of debug exceptions on CP15 registers and DBGWFAR
The four CP15 registers that record abort information are:
1. c5, Data Fault Status Register on page 4-48
2. c5, Instruction Fault Status Register on page 4-49
3. c6, Data Fault Address Register on page 4-51
4. c6, Instruction Fault Address Register on page 4-51
If the processor takes a debug exception because of a watchpoint debug event, the processor
performs the following actions on these registers:
• it does not change the IFSR or IFAR
• it updates the DFSR with the debug event encoding
• it writes an Unpredictable value to the DFAR
• it updates the DBGWFAR with the address of the instruction that accessed the
watchpointed address, plus a processor state dependent offset:
— + 8 for ARM state
— + 4 for Thumb state.
If the processor takes a debug exception because of a breakpoint,
BKPT , or vector catch debug
event, the processor performs the following actions on these registers:
• it updates the IFSR with the debug event encoding
• it writes an Unpredictable value to the IFAR
• it does not change the DFSR, DFAR, or DBGWFAR.
12.7.2 Avoiding unrecoverable states
The processor ignores vector catch debug events on the Prefetch or Data Abort vectors while in
Monitor debug-mode because these events would otherwise put the processor in an
unrecoverable state.
Table 12-40 Values in link register after exceptions
Cause of fault ARM Thumb
Return address (RA
a
) meaning
a. This is the address of the instruction that the processor can execute first on debug exception return. The
address of the access that hit the watchpoint is in the DBGWFAR.
Breakpoint RA+4 RA+4 Breakpointed instruction address
Watchpoint RA+8 RA+8 Watchpointed instruction address
BKPT instruction RA+4 RA+4 BKPT instruction address
Vector catch RA+4 RA+4 Vector address
Prefetch Abort RA+4 RA+4 Address of the instruction where the execution can resume
Data Abort RA+8 RA+8 Address of the instruction where the execution can resume