System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-48
ID073015 Non-Confidential
c5, Data Fault Status Register
The DFSR characteristics are:
Purpose Holds status information regarding the source of the last data abort.
Usage constraints The DFSR is:
• a read/write register
• accessible in Privileged mode only.
Configurations Available in all processor configurations.
Attributes See Table 4-28.
Figure 4-30 shows the DFSR bit assignments.
Figure 4-30 DFSR Register bit assignments
Table 4-28 shows the DFSR bit assignments.
To use the DFSR read or write CP15 with:
MRC p15, 0, <Rd>, c5, c0, 0 ; Read DFSR
MCR p15, 0, <Rd>, c5, c0, 0 ; Write DFSR
Domain
0
Reserved
31 8 7 4 3 0
Status
9
0S
10111213
RW
SD
Table 4-28 DFSR Register bit assignments
Bits Name Function
[31:13] - SBZ.
[12] SD Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid
for external aborts. For all other aborts types of abort, this bit is set to zero:
0
= AXI Decode error (DECERR) caused the abort
1
= AXI Slave error (SLVERR, or OKAY in response to exclusive read transaction) caused the
abort.
[11] RW Indicates whether a read or write access caused an abort:
0
= read access caused the abort
1
= write access caused the abort.
[10]
a
S Part of the Status field.
[9:8] - Always RAZ. Writes ignored.
[7:4] Domain SBZ. This is because domains are not implemented in this processor.
[3:0]
a
Status Indicates the type of fault generated. To determine the data fault, you must use bit [12] and bit [10]
in conjunction with bits [3:0].
a. For more information on how these bits are used in reporting faults, see Table 4-27 on page 4-47.
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