ARM Cortex-R4 - C.9 Branches

Cycle Timings and Interlock Behavior
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. C-15
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C.9 Branches
This section describes the cycle timing behavior for the B , BL , BLX , BX , BXJ , CBNZ , CBZ , TBB , and TBH
instructions. Branches are subject to dynamic and return stack predictions. Table C-10 shows
example branch instructions and their cycle timing behavior.
Table C-10 Branch instruction cycle timing behavior
Example instruction Cycles
Memory
cycles
Comments
B<label>, BL<label>a,
BLX<label>
a
1 - Correct dynamic prediction
8 - Incorrect dynamic prediction
BX <Rm>
b
1 - Correct return stack prediction
9 - Incorrect return stack prediction
BX <cond> <Rm>
b
1 - Correct condition prediction and correct return stack prediction
8 - Incorrect condition prediction
9 - Correct condition prediction and incorrect return stack prediction
BXJ <cond> <Rm> 1 - Condition code fails
9 - Condition code passes
BLX <Rm> 9- -
BLX <cond> <Rm> 1 - Condition code fails
9 - Condition code passes
CBZ <Rn>, <label> , CBNZ
<Rn>, <label>
1 - Correct condition prediction
8 - Incorrectly predicted
TBB [<Rn>, <Rm>]
c
9 1 Condition code fails
9 1 Condition code passes
TBH [<Rn>, <Rm>, LSL#1]
c
9 1 Condition code fails
9 1 Condition code passes
a. Return stack push.
b. Return stack pop, if condition passes.
c.
<Rn> and <Rm> are Very Early Regs.