ARM Cortex-R4 - 1.4 Interfaces

Introduction
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1.4 Interfaces
The processor has the following interfaces:
• 64-bit AXI master interface, for instruction fetch and data access
• 64-bit AXI slave interface, for external access to TCMs and cache RAMs
• TCM interface, for access to local memory containing instructions and data
• VIC interface, for the connection of a PL192 VIC
• configuration signals for customizing the behavior of the processor, particularly from
reset
• interrupt outputs providing information about the behavior of the processor to the wider
system
• 32-bit APB slave interface and various debug handshake signals, for connection to
CoreSight components providing debug features
• ETM interface, for connection to a CoreSight ETM-R4 providing instruction and data
trace
• Memory Built-In Self Test (MBIST) interface and scan signals, enabling test during
manufacture of local RAMs and logic.
All the processor AMBA interfaces conform to one of the following AMBA 3 specifications:
• AMBA AXI Protocol Specification
• AMBA APB Protocol Specification.
The debug interfaces are CoreSight compliant, see the CoreSight Architecture Specification.