Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-10
ID073015 Non-Confidential
12.4 Debug register descriptions
Table 12-5 shows definitions of terms used in the register descriptions.
12.4.1 Accessing debug registers
To access the CP14 debug registers you set Opcode_1 and Opcode_2 to zero. The CRn and
CRm fields of the coprocessor instructions encode the CP14 debug register number, where the
register number is
{<Opcode2>, <CRm>}
. In addition, the CRn field can specify additional
registers.
Table 12-6 shows the CP14 debug register map.
12.4.2 CP14 c0, Debug ID Register
The DBGDIDR Register characteristics are:
Purpose Identifies the debug architecture version and specifies the number of
debug resources that the processor implements.
Table 12-5 Terms used in register descriptions
Term Description
R Read-only. Written values are ignored.
W Write-only. This bit cannot be read. Reads return an Unpredictable value.
RW Read or write.
RAZ Read-As-Zero. Always zero when read.
RAO Read-As-One. Always one when read.
SBZP Should-Be-Zero (SBZ) or Preserved (P). Must be written as 0 or preserved by writing the same value previously
read from the same fields on the same processor. These bits are usually reserved for future expansion.
UNP A read from this bit returns an Unpredictable value.
Table 12-6 CP14 debug register map
CRn Op1 CRm Op2 CP14 debug register name Abbreviation Reference
c0 0 c0 0 Debug ID Register DBGDIDR CP14 c0, Debug ID Register
c1 0 c0 0 Debug ROM Address Register DBGDRAR CP14 c0, Debug ROM Address
Register on page 12-12
c2 0 c0 0 Debug Self Address Offset
Register
DBGDSAR CP14 c0, Debug Self Address
Offset Register on page 12-13
c3-c15 0 c0 0 Reserved - -
c0 0 c1 0 Debug Status and Control
Register
DBGDSCR CP14 c1, Debug Status and
Control Register on page 12-14
c1-c15 0 c1 0 Reserved - -
c0-c15 0 c2-c4 0 Reserved - -
c0 0 c5 0 Data Transfer Register DTR Data Transfer Register on
page 12-18
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