ARM Cortex-R4 - Page 283

Debug
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 12-9
ID073015 Non-Confidential
Locks permission
You can lock the APB slave port so that access to some debug registers is restricted. ARM
architecture v7 defines two locks:
Software lock
The external debugger can set this lock to prevent software from modifying the
debug registers settings. A debug monitor can also set this lock prior to returning
control to the application to reduce the chance of erratic code changing the debug
settings. When this lock is set, writes to all debug registers are ignored, except
those generated by the external debugger, that override the lock. For more
information, see Lock Access Register on page 12-38.
OS Lock The processor does not support OS Lock.
Note
• These locks are set to their reset values only on reset of the debug logic, provided by
PRESETDBGn.
• You must set the PADDRDBG31 input signal to 1 for accesses originated from the
external debugger for the Software Lock override feature to work.
Table 12-4 External debug interface access permissions
Registers
PADDRDBG31 Lock
DBGDRCR,
DBGPRCR,
DBGPRSR
Other Debug registers LAR Other registers
X
X
a
NPOSS
b
NPOSS
b
NPOSS
b
NPOSS
b
1
X
a
OK
c
OK
c
OK
c
OK
c
0
1
d
WI
e
WI
e
OK
c
WI
e
00
OK
c
OK
c
OK
c
OK
c
a. X indicates that the outcome does not depend on this condition.
b. Not possible. Accessing debug registers while the processor is powered down is not possible.
c. OK indicates that the access succeeds.
d. LSR[1] bit is set.
e. WI indicates that writes are ignored.