ARM Cortex-R4 - Exception Vectors

Programmers Model
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 3-24
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Note
If the debug logic is configured into Halting debug-mode, a breakpoint instruction causes the
processor to enter debug state. See Halting debug-mode debugging on page 12-3.
3.7.8 Exception vectors
You can configure the location of the exception vector addresses by setting the V bit in CP15
c1 SCTLR to enable HIVECS, as Table 3-5 shows.
Table 3-6 shows the exception vector addresses and entry conditions for the different exception
types.
Table 3-5 Configuration of exception vector address locations
Value of V bit
Exception vector
base location
0
0x00000000
1 (HIVECS) 0xFFFF0000
Table 3-6 Exception vectors
Exception
Offset from
vector base
Mode on entry A bit on entry F bit on entry I bit on entry
Reset
0x00 Supervisor Set Set Set
Undefined instruction
0x04 Undefined Unchanged Unchanged Set
Software interrupt
0x08 Supervisor Unchanged Unchanged Set
Abort (prefetch)
0x0C Abort Set Unchanged Set
Abort (data)
0x10 Abort Set Unchanged Set
IRQ
0x18 IRQ Set Unchanged Set
FIQ
0x1C FIQ Set Set Set