Integration Test Registers
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 13-4
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13.3 Processor integration testing
This section describes the behavior and use of the Integration Test Registers that are in the
processor. It also describes the Integration Mode Control Register that controls the use of the
Integration Test Registers. For more information about the DBGITCTRL, see the ARM
Architecture Reference Manual.
If you want to access these registers you must first set bit [0] of the Integration Mode Control
Register to 1.
• You can use the write-only Integration Test Registers to set the outputs of some of the
processor signals. Table 13-2 shows the signals that you can write in this way.
• You can use the read-only Integration Test Registers to read the state of some of the
processor inputs. Table 13-3 on page 13-5 shows the signals that you can read in this way.
There are Integration Test Registers that you can use in conjunction with ETM-R4 integration.
For more information, see the ETM-R4 Technical Reference Manual.
Table 13-2 Output signals that can be controlled by the Integration Test Registers
Signal Register Bit Register description
DBGRESTARTED DBGITMISCOUT [9] See DBGITMISCOUT Register (Miscellaneous Outputs) on
page 13-7
DBGTRIGGER DBGITMISCOUT [8]
ETMWFIPENDING DBGITMISCOUT [5]
nPMUIRQ DBGITMISCOUT [4]
COMMTX DBGITMISCOUT [2]
COMMRX DBGITMISCOUT [1]
DBGACK DBGITMISCOUT [0]
EVNTBUS[46] DBGITETMIF [14] See DBGITETMIF Register (ETM interface) on page 13-6
EVNTBUS[28, 0] DBGITETMIF [13:12]
ETMCID[31, 0] DBGITETMIF [11:10]
ETMDA[31, 0] DBGITETMIF [7:6]
ETMDCTL[11, 0] DBGITETMIF [5:4]
ETMDD[63, 0] DBGITETMIF [9:8]
ETMIA[31, 1] DBGITETMIF [3:2]
ETMICTL[13, 0] DBGITETMIF [1:0]
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