ARM Cortex-R4 - C.4 QADD, QDADD, QSUB, and QDSUB instructions

Cycle Timings and Interlock Behavior
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C.4 QADD, QDADD, QSUB, and QDSUB instructions
This section describes the cycle timing behavior for the QADD , QDADD , QSUB , and QDSUB instructions.
These instructions perform saturating arithmetic. They have a result latency of two. The
QDADD
and
QDSUB instructions must double and saturate the register <Rn> before the addition. This
register is an Early Reg.
Table C-5 shows the cycle timing behavior for
QADD , QDADD , QSUB , and QDSUB instructions.
Table C-5 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior
Instructions Cycles Early Reg Result latency
QADD , QSUB 1- 2
QDADD , QDSUB 1 <Rn> 2