ARM Cortex-R4 - 4.1 About system control

System Control
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 4-2
ID073015 Non-Confidential
4.1 About system control
This section gives an overview of the system control coprocessor. It contains the following
sections:
• System identification control and configuration
• MPU control and configuration on page 4-3
• Cache control and configuration on page 4-3
• Interface control and configuration on page 4-4
• System performance monitor on page 4-4
• System validation on page 4-5.
The purpose of the system control coprocessor, CP15, is to control and provide status
information for the functions implemented in the processor.
The system control coprocessor does not exist in a distinct physical block of logic.
4.1.1 System identification control and configuration
The system identification control and configuration registers provide overall management of:
• memory functionality
• interrupt behavior
• exception handling
• program flow prediction
• coprocessor access rights for CP0-CP13, including the VFP, CP10-11.
The system identification control and configuration registers also provide the processor ID and
information on configured options.
The system identification control and configuration registers consist of 18 read-only registers
and seven read/write registers. Figure 4-1 shows the arrangement of registers in this functional
group.
Figure 4-1 System control and configuration registers
Some of the functionality depends on how you set external signals at reset.
CRn
c1
Coprocessor Access Register
Auxiliary Control Register
System Control Register
1
0c00
c13
0
c0
Context ID Register
0
Opcode_2CRmOpcode_1
c0
Main ID Register
0
c00
Debug Feature Register 0
Auxiliary Feature Register 0
{0, 1}
Processor Feature Registers 0, 1
Multiprocessor ID Affinity Register
Memory Model Feature Registers 0 - 3
Instruction Set Attributes Registers 0 - 5
c1
5
2
3
{4–7}
{0-5}
c2
2
Write-only
Accessible in User mode
Read-only Read/write
FCSE PID Register
1
c15
00 c0
c2
0
1
Secondary Auxiliary Control Register
Build Options Register 1
Build Options Register 2