Functional Description
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-6
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The ETM interface collects various processor signals and drives these signals from the
processor. The interface is unidirectional and runs at the full speed of the processor. The ETM
interface connects directly to the external ETM unit without any additional glue logic. You can
disable the ETM interface for power saving. For more information, see the CoreSight ETM-R4
Technical Reference Manual.
Real-time debug facilities
The processor contains debug logic, that can be used in a CoreSight system to support the debug
operation. It supports:
• up to eight breakpoints
• up to eight watchpoints
•a Debug Communications Channel (DCC).
The number of breakpoints and watchpoints is configured during implementation, see
Configurable options on page 1-6.
The debug logic monitors the internal address and data buses. You access the debug logic
through the memory-mapped APB interface.
The processor implements the ARMv7 Debug architecture.
See Chapter 12 Debug for more information on debug.
The debug logic supports two modes of debug operation:
Halting debug-mode
On a debug event, such as a breakpoint or watchpoint, the debug logic stops the
processor and forces it into debug state. This enables you to examine the internal
state of the processor, and the external state of the system, independently from
other system activity. When the debugging process completes, the processor and
system state are restored, and normal program execution resumes.
Monitor debug-mode
On a debug event, the processor generates a debug exception instead of entering
debug state, as in halting debug-mode. The exception entry enables a debug
monitor program to debug the processor while enabling critical interrupt service
routines to operate on the processor. The debug monitor program can
communicate with the debug host over the DCC or any other communications
interface in the system.
2.1.7 System control coprocessor
The system control coprocessor provides configuration and control of the memory system and
its associated functionality. Other system-level operations, such as cache maintenance
operations, are also managed through the system control coprocessor.
For more information, see System identification control and configuration on page 4-2.
2.1.8 Interrupt handling
Interrupt handling in the processor is compatible with previous ARM architectures, but has
several additional features to improve interrupt performance for real-time applications.
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