ARM Cortex-R4 - System Validation

To Next Page

To Previous Page

System Control

ID073015 Non-Confidential

Figure 4-5 System performance monitor registers

System performance monitoring counts system events, such as cache misses, pipeline stalls, and

other related features to enable system developers to profile the performance of their systems.

It can generate interrupts when the number of events reaches a given value.

For more information on the programmers model of the performance counters see the ARM

Architecture Reference Manual. See Chapter 6 Events and Performance Monitor for more

information on the registers.

4.1.6 System validation

The system validation registers extend the use of the system performance monitor registers to

provide some functions for validation. You must not use them for other purposes. The system

validation registers schedule and clear:

• resets

• interrupts

• fast interrupts

• external debug requests.

The system validation registers consist of nine read/write registers and one write-only register.

Figure 4-6 shows the arrangement of registers.

Figure 4-6 System validation registers

Opcode_2CRmCRn Opcode_1

00 c12

Overflow Flag Status Register †

Count Enable Set Register †

Count Enable Clear Register †

Performance Monitor Control Register †

Event Select Register †

Performance Counter Selection Register †

Cycle Count Register †

Software Increment Register †

Interrupt Enable Clear Register

User Enable Register

Interrupt Enable Set Register

Performance Count Register †

c13

c140

Write-only

Accessible in User mode

Read-only

Read/write

† If enabled in User

Enable Register

c15

Opcode_2Opcode_1 CRmCRn

nVAL IRQ Enable Set Register †

nVAL FIQ Enable Set Register †

nVAL Reset Enable Set Register †

nVAL Debug Request Enable Set Register †

nVAL IRQ Enable Clear Register †

nVAL FIQ Enable Clear Register †

nVAL Debug Request Enable Clear Register †

Cache size override register

nVAL Reset Enable Clear Register †