Memory Protection Unit
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 7-10
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7.5 MPU faults
The MPU can generate three types of fault:
• Background fault
• Permission fault
• Alignment fault.
When a fault occurs, the memory access or instruction fetch is precisely aborted, and a prefetch
abort or data abort exception is taken as appropriate. No memory accesses are performed on the
AXI bus master interface. For more information about fault handling, see Fault handling on
page 8-7.
7.5.1 Background fault
A background fault is generated when the MPU is enabled and a memory access is made to an
address that is not within an enabled subregion of an MPU region. A background fault does not
occur if the background region is enabled and the access is Privileged. See Background regions
on page 7-6.
7.5.2 Permission fault
A permission fault is generated when a memory access does not meet the requirements of the
permissions defined for the memory region that it accesses. See Region access permissions on
page 7-4.
7.5.3 Alignment fault
An alignment fault is generated if a data access is performed to an address that is not aligned for
the size of the access, and strict alignment is required for the access. A number of instructions
that access memory, for example,
LDM
and
STC
, require strict alignment. See the ARM
Architecture Reference Manual for information. In addition, strict alignment can be required for
all data accesses by setting the A-bit in the SCTLR. See c1, System Control Register on
page 4-37.
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