ARM Cortex-R4 - C.10 Processor state updating instructions

Cycle Timings and Interlock Behavior
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C.10 Processor state updating instructions
This section describes the cycle timing behavior for the MSR , MRS , CPS , and SETEND instructions.
Table C-11 shows processor state updating instructions and their cycle timing behavior.
Table C-11 Processor state updating instructions cycle timing behavior
Instruction Cycles Comments
MRS 1All MRS instructions
MSR 5 All other MSR instructions to the CPSR
MSR SPSR 1All MSR instructions to the SPSR
CPS <effect> <iflags> 1 Interrupt masks only
CPS <effect> <iflags>, #<mode> 1 Mode changing
SETEND 1-