ARM Cortex-R4 - 13.2 Summary of the processor registers used for integration testing

Integration Test Registers
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13.2 Summary of the processor registers used for integration testing
Table 13-1 lists the processor Integration Test Registers and the Integration Mode Control
Register, DBGITCTRL.
Table 13-1 Integration Test Registers summary
Register name
Base
offset
Default
value
Type
Clock
domain
Description
Integration Test Registers
DBGITETMIF 0xED8
-
a
WO CLK See DBGITETMIF Register (ETM interface) on
page 13-6
DBGITMISCOUT
0xEF8 n/a WO CLK See DBGITMISCOUT Register (Miscellaneous
Outputs) on page 13-7
DBGITMISCIN
0xEFC
-
a
RO CLK See DBGITMISCIN Register (Miscellaneous
Inputs) on page 13-7
Integration Mode Control Register
DBGITCTRL 0xF00 0 R/W CLK See Integration Mode Control Register on
page 13-8
a. See the register description for this value.