Functional Description
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 2-9
ID073015 Non-Confidential
2.2 Interfaces
The processor has the following interfaces for external access:
• AXI master interface
• AXI slave interface
• TCM interfaces
• Interrupt and VIC interface
• Configuration interface
• Interrupt and event outputs
• APB Debug interface
• ETM interface on page 2-10
• Test interface on page 2-10.
2.2.1 AXI master interface
AXI master interface on page 9-3 describes the AXI master interface. AXI master port on
page A-8 and AXI master port error detection signals on page A-10 describe the associated
signals. The AMBA AXI Protocol Specification describes the AXI protocol.
2.2.2 AXI slave interface
AXI slave interface on page 9-20 describes the AXI slave interface. AXI slave port on page A-11
and AXI slave port error detection signals on page A-12 describe the associated signals. The
AMBA AXI Protocol Specification describes the AXI protocol.
2.2.3 TCM interfaces
About the TCMs on page 8-13 describes the TCM interfaces. TCM interface signals on
page A-13 describes the associated signals.
2.2.4 Interrupt and VIC interface
Interrupts on page 3-16 describes the interrupts. Interrupt signals, including VIC interface
signals on page A-7 describes the associated signals.
2.2.5 Configuration interface
Configuration signals on page A-4 describes the configuration signals.
2.2.6 Interrupt and event outputs
Chapter 6 Events and Performance Monitor describes events and the interrupts they can
generate. Exceptions on page 11-14 describes the FPU exception outputs. Interrupt signals,
including VIC interface signals on page A-7, ETM interface signals on page A-19, Validation
signals on page A-22, and FPU signals on page A-23 describe the associated signals.
2.2.7 APB Debug interface
AMBA APBv3 is used for debugging purposes. CoreSight is the ARM architecture for
multi-processor trace and debug. CoreSight defines what debug and trace components are
required and how they are connected. See the CoreSight Architecture Specification for more
information
. Debug interface signals on page A-17 describes the debug APB interface signals.
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