FPU Programmers Model
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. 11-14
ID073015 Non-Confidential
11.5.3 Exceptions
The FPU implements the VFPv3 architecture and sets the cumulative exception status flag in
the FPSCR register as required for each instruction. The FPU does not support user-mode traps.
The exception enable bits in the FPSCR read-as-zero, and cannot be written. The processor also
has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect
the status of one of the cumulative exception flags. See FPU signals on page A-23 for a
description of these outputs. You can mask each of these outputs masked by setting the
corresponding bit in the Secondary Auxiliary Control Register.
See c1, Auxiliary Control Register on page 4-40 for more information.
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